Integration process flow for flash devices with low gap fill aspect ratio

1. A method of making a memory system on a semiconductor substrate, comprising:

forming a plurality of shallow trench isolation structures separating floating gate structures;

implanting ions into the plurality of shallow trench isolation structures;

etching the plurality of shallow trench isolation structures such that portions of shallow trench isolation structures that have a high concentration of implanted ions etch faster than portions of shallow trench isolation structures that have a low concentration of implanted ions; and

stopping etching the plurality of shallow trench isolation structures at a depth where the concentration of implanted ions is less than a maximum concentration and where the etch rate is decreasing with increasing etch depth, wherein hard-mask portions define locations of the shallow trench isolation structures and, after the defining locations of shallow trench isolation structures, the hard-mask portions are replaced with conductive floating gate portions.

2. The method of claim 1 further comprising forming an electrically conductive polysilicon layer overlying the plurality of shallow trench isolation structures prior to implanting ions across the substrate.

3. The method of claim 2 wherein the conductive polysilicon layer is planarized prior to implanting ions.

4. The method of claim 1 wherein the semiconductor substrate includes a memory array and a peripheral area and individual shallow trench isolation structures are present in both the memory array and the peripheral area.

5. A method of making a memory system on a semiconductor substrate including a memory array in a memory array region and peripheral circuits in a peripheral region, comprising:

forming a plurality of shallow trench isolation structures in both the memory array region and the peripheral region, shallow trench isolation structures of the peripheral region being larger than shallow trench isolation structures of the array region;

implanting ions across the substrate including the plurality of shallow trench isolation structures;

etching the plurality of shallow trench isolation structures with an etch that etches portions of shallow trench isolation structures that have a high concentration of implanted ions faster than it etches portions of shallow trench isolation structures that have a low concentration of implanted ions;

stopping etching the plurality of shallow trench isolation structures at a depth where the concentration of implanted ions is less than a maximum concentration and where the etch rate is decreasing with increasing etch depth; and

forming floating gates in the memory array region, the floating gates separated by the shallow trench isolation structures prior to etching, upper portions of shallow trench isolation structures directly between floating gates being removed by the etching, a dielectric layer and control gate subsequently formed that extend directly between floating gates where the upper portions of shallow trench isolation structures are removed.

6. The method of claim 5 further comprising forming an electrically conductive polysilicon layer overlying the plurality of shallow trench isolation structures prior to implanting ions across the substrate.

7. A method of planarizing a substrate for memory devices, comprising:

forming a plurality of first conductive portions separated by shallow trench isolation structures, the shallow trench isolation structures extending above an upper surface of the plurality of first conductive portions;

forming a plurality of second conductive portions, an individual second conductive portion extending partially over an upper surface of a first conductive portion and partially over a shallow trench isolation structure;

subsequently forming a conductive layer that extends across the substrate including the second conductive portions;

planarizing the conductive layer by removing portions of the conductive layer that extend higher than an upper surface of a portion of the conductive layer that directly overlies a shallow trench isolation structure; and

implanting ions through the planarized conductive layer into the shallow trench isolation structures.

8. The method of claim 7 wherein removing portions of the conductive layer that extend higher than an upper surface of a portion of the conductive layer that directly overlies a shallow trench isolation structure is by chemical mechanical polishing.

9. The method of claim 8 wherein the chemical mechanical polishing is performed with a pressure between the substrate and a pad that erodes the portions of the conductive layer that extend higher than an upper surface of a portion of the conductive layer that directly overlies a shallow trench isolation structure while not significantly eroding the upper surface of the portion of the conductive layer that directly overlies the shallow trench isolation structure.

10. The method of claim 7 further comprising subsequently removing the first conductive layer and subsequently etching portions of the shallow trench isolation structures that have an implanted ion concentration above a threshold value but not removing portions of the shallow trench isolation structures that have an implanted ion concentration below the threshold value.

11. The method of claim 7 wherein the conductive layer is formed in direct contact with the plurality of second conductive portions.

12. The method of claim 7 wherein individual second conductive portions are wider than individual first conductive portions.