Non-volatile memory with compensation for variations along a word line
Variation in programming efficacy due to variation in time constants along a word line that spans across a memory plane is compensated by adjusting the bit line voltages across the plane to modify the programming rates. In this way, the variation in programming efficacy is substantially reduced during programming of a group of memory cells coupled to the word line. This will allow uniform optimization of programming across the group of memory cells and reduce the number of programming pulses required to program the group of memory cells, thereby improving performance. In one embodiment, during programming, the bit lines in a first half of the memory plane closer to a source of word line voltage is set to a first voltage and the bit lines in a second half of the memory plane further from the source of word line voltage is set to a second voltage.
1. A non-volatile memory, comprising:
an array of memory cells in a memory plane;
a group of memory cells coupled to a word line spanning across the memory plane, each memory cell of the group accessible by a bit line in a column of the memory plane,
an access node to the word line for applying a programming voltage thereto, with each memory cell of the group being at a corresponding distance of the word line relative to the access node;
the memory plane being partitioned into a plurality of columnar portions, each portions contains a set of bit lines;
an independent voltage source for each set of bit lines for supplying a bit line voltage as a function of the corresponding distance from the access node; and
wherein the programming voltage comprises a series of voltage pulses.
2. The non-volatile memory as in claim 1 , wherein the voltage pulses increase in amplitude with every pulse.
3. The non-volatile memory as in claim 1 , wherein:
each memory cell of the group receives the programming voltage from the access node through a corresponding RC network defined by the corresponding distance of the word line relative to the access node.
4. The non-volatile memory as in claim 3 , wherein:
the programming voltage received by each memory cell has a programming efficacy modified by finite charging and discharging time due to the corresponding RC network; and
said independent voltage source for each set of bit lines supplying a bit line voltage as a function of the corresponding distance from the access node compensates for the modified programming efficacy.
5. A non-volatile memory, comprising:
an array of memory cells in a memory plane;
a group of memory cells coupled to a word line spanning across the memory plane, each memory cell of the group accessible by a bit line in a column of the memory plane,
an access node to the word line for applying a programming voltage thereto, with each memory cell of the group being at a corresponding distance of the word line relative to the access node;
the memory plane being partitioned into a plurality of columnar portions, each portions contains a set of bit lines;
an independent voltage source for each set of bit lines for supplying a bit line voltage as a function of the corresponding distance from the access node; and
wherein the word line is divided into two halves with a first half closer to the access node and a second half further from the access node; and
the function is such that it produces a first bit line voltage for memory cells coupled to the first half and a second bit line voltage for memory cells coupled to the second half of the word line.
6. The non-volatile memory as in claim 5 , wherein the second bit line voltage is at a ground potential.
7. A non-volatile memory, comprising:
an array of memory cells in a memory plane;
a group of memory cells coupled to a word line spanning across the memory plane, each memory cell of the group accessible by a bit line in a column of the memory plane,
an access node to the word line for applying a programming voltage thereto, with each memory cell of the group being at a corresponding distance of the word line relative to the access node;
the memory plane being partitioned into a plurality of columnar portions, each portions contains a set of bit lines;
an independent voltage source for each set of bit lines for supplying a bit line voltage as a function of the corresponding distance from the access node; and
wherein the word line is divided into multiple portions; and
the function is such that it produces a distinct bit line voltage for memory cells coupled to each portion of the word line.