IP Library Granted Patent US 7,737,539
Granted Patent B2
US 7,737,539 · App. 11/306,854 · Granted Jun 15, 2010

Integrated circuit package system including honeycomb molding

Assignee: STATS Chippac Ltd.
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Quick Facts
Patent No.
US 7,737,539
App. No.
11/306,854
Granted
Jun 15, 2010
Kind
B2
Abstract

An integrated circuit package system including a substrate with a top surface and a bottom surface. Configuring the top surface to include electrical contacts formed between a perimeter of the substrate and a semiconductor die. Aligning over the top surface of the substrate a mold plate with a honeycomb meshwork of posts or a stepped honeycomb meshwork of posts and depositing a material to prevent warpage of the substrate between the top surface of the substrate and the mold plate. Removing the mold plate to reveal discrete hollow conduits formed within the material that align with the electrical contacts.

Claims (53)

1. A method of manufacture of an integrated circuit package system comprising:

providing a substrate with a top surface and a bottom surface;

configuring the top surface to include electrical contacts formed between a perimeter of the substrate and a semiconductor die;

aligning over the top surface of the substrate a mold plate;

depositing a material to prevent warpage of the substrate between the top surface of the substrate and the mold plate; and

removing the mold plate to reveal stepped discrete hollow conduits formed within the material that align with the electrical contacts.

2. The method as claimed in claim 1 wherein:

depositing the material includes top center gate molding, conventional side molding or conventional corner molding techniques.

3. The method as claimed in claim 1 wherein:

configuring the electrical contacts includes the electrical contacts selected from shapes including circles, squares, hexagons, and combinations thereof.

4. The method as claimed in claim 1 further comprising:

forming external electrical connections on the bottom surface of the substrate.

5. The method as claimed in claim 1 further comprising:

configuring the integrated circuit package system to include a package-on-package configuration or a package-in-package configuration.

6. A method of manufacture of an integrated circuit package system comprising:

providing a first package with a first substrate;

configuring the first substrate to include a first top surface including first electrical contacts and a first bottom surface including first external electrical connections;

depositing a first material between the first substrate and a first mold plate formed over the first substrate;

removing the first mold plate to reveal first stepped discrete hollow conduits formed within the first material that are aligned over the first electrical contacts of the first substrate; and

providing a second package with a second substrate and a second material formed over and electrically connected to the first package through the first stepped discrete hollow conduits.

7. The method as claimed in claim 6 further comprising:

depositing the second material between the second substrate and a second mold plate formed over the second substrate; and

removing the second mold plate to reveal second discrete hollow conduits formed within the second material over the second substrate.

8. The method as claimed in claim 7 wherein:

removing the second mold plate formed over the second substrate includes revealing stepped discrete hollow conduits.

9. The method as claimed in claim 6 wherein:

depositing the first material and the second material provides structural integrity to the first substrate and the second substrate that prevents warping during subsequent processing.

10. An integrated circuit package system comprising:

a substrate with a top surface and a bottom surface;

the top surface includes electrical contacts formed between a perimeter of the substrate and a semiconductor die;

a material that prevents warpage of the substrate over the top surface of the substrate; and

stepped discrete hollow conduits within the material that are aligned over the electrical contacts.

11. The system as claimed in claim 10 further comprising:

external electrical connections formed on the bottom surface of the substrate.

12. The system as claimed in claim 10 wherein:

the electrical contacts are selected from shapes including circles, squares, hexagons, and combinations thereof.

13. The system as claimed in claim 10 wherein:

the substrate is part of a first package and a second package is formed thereover.

14. The system as claimed in claim 10 wherein:

the integrated circuit package system includes forming a package-on-package configuration or a package-in-package configuration.

15. An integrated circuit package system comprising:

a first package with a first substrate including a first top surface and a first bottom surface;

first electrical contacts formed on the first top surface of the first substrate and first external electrical connections formed on the first bottom surface of the first substrate;

a first material over the first substrate for preventing warpage of the first substrate having first stepped discrete hollow conduits formed within and over the first substrate; and

a second package including a second substrate and a second material formed over and electrically connected to the first package through the first stepped discrete hollow conduits.

16. The system as claimed in claim 15 wherein:

the second material includes second discrete hollow conduits formed within and over the second substrate.

17. The system as claimed in claim 16 wherein:

the second discrete hollow conduits are selected from shapes including circles, squares, hexagons, and combinations thereof.

18. The system as claimed in claim 15 further comprising:

additional packages formed over the second package.

19. The system as claimed in claim 15 wherein:

the first discrete hollow conduits are selected from shapes including circles, squares, hexagons, and combinations thereof.

Assignments (8)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 3, 2025
From: STATS CHIPPAC PTE. LTD.
To: STATS CHIPPAC MANAGEMENT PTE. LTD.
Reel/Frame 072788/0917 →
CORRECTIVE ASSIGNMENT TO CORRECT THE CONVEYING PARTY DATA FROM STATS CHIPPAC PTE. LTE. TO STATS CHIPPAC LTD. AND CORRECT THE NAME OF RECEIVING PARTY DATA FROM STATS CHIPPAC PTE. LTE. TO STATS CHIPPAC PTE. LTD. PREVIOUSLY RECORDED AT REEL: 64838 FRAME: 948. ASSIGNOR(S) HEREBY CONFIRMS THE CHANGE OF NAME. Recorded May 29, 2024
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 067534/0872 →
CORRECT ERROR IN ASSIGNMENT NAME FROM STATS CHIPPAC PTE. LTE. TO STATS CHIPPAC PTE. LTD. (REEL: 038378 FRAME: 0328 Recorded Aug 30, 2023
From: STATS CHIPPAC PTE. LTE.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 064838/0948 →
RELEASE OF SECURITY INTEREST Recorded Jun 15, 2020
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 052935/0327 →
CHANGE OF NAME Recorded Apr 7, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0328 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 1, 2010
From: KWON, HYEOG CHAN; KIM, HYUN JOUNG; KIM, JAE CHANG; LIM, TAEG KI; JU, JONG WOOK
To: STATS CHIPPAC LTD.
Reel/Frame 024177/0251 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 12, 2006
From: KWON, HYEOG CHAN; KIM, HYUN JOUNG; KIM, JAE CHANG; LIM, TAEG KI; JU, JONG WOOK
To: STATS CHIPPAC LTD.
Reel/Frame 017010/0744 →
Continuity (1)
Related Publication 20070158806A1 · Jul 12, 2007