IP Library Granted Patent US 7,759,902
Granted Patent B2
US 7,759,902 · App. 11/335,057 · Granted Jul 20, 2010

Single chip microcontroller including battery management and protection

Assignee: Atmel Corporation
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Quick Facts
Patent No.
US 7,759,902
App. No.
11/335,057
Granted
Jul 20, 2010
Kind
B2
Abstract

A microcontroller is disclosed. The microcontroller comprises a processor system and a high voltage interface coupled to the processor system and adapted to be coupled to a battery. The microcontroller further includes a battery management system for monitoring the battery and managing the battery based upon the monitoring of the battery. The microcontroller is a single chip. This one-chip solution saves design cost and PCB space in addition to broadening the functionality of the smart battery application. With the accuracy of the microcontroller, the charge status of the battery can be predicted more accurately and therefore effectively increases actual battery capacity.

Claims (46)

1. A microcontroller comprising:

a processor system including a data bus;

a system management bus (SMBus) interface;

a high voltage battery interface coupled to the processor system, wherein a battery to be coupled to the high voltage battery interface comprises a plurality of cells, wherein the high voltage battery interface includes a plurality of inputs to the microcontroller capable of operating in a range of 4 volts to 25 volts; and

a battery management system to monitor the battery and to manage the battery based upon monitoring of the battery,

wherein the battery management system includes a control system to control charging and discharging of the battery,

wherein the control system includes a plurality of cell-balancing FETs coupled to the plurality of cells and to the data bus,

wherein there is one cell-balancing FET among the plurality of cell-balancing FETs coupled to each cell of the plurality of cells, and

wherein each cell balancing FET of the plurality of cell-balancing FETs is directly controlled by reprogrammable application software via a control register coupled to the data bus; and

wherein the microcontroller is a single chip.

2. The microcontroller of claim 1 , wherein the battery management system includes a battery protection circuit to detect at least one illegal condition on the battery and to protect the battery from the at least one illegal condition.

3. The microcontroller of claim 2 , wherein the at least one illegal condition comprises at least one of: a deep under-voltage during discharging, a short circuit during discharging, and an over-current during charging or discharging.

4. The microcontroller of claim 1 , wherein the processor system further comprises:

a central processing unit (CPU).

5. The microcontroller of claim 1 , wherein the battery management system further comprises:

a voltage regulator adapted to be coupled to the battery via the high voltage battery interface, wherein the voltage regulator is to regulate a supply voltage to the microcontroller at a predetermined level.

6. The microcontroller of claim 5 , wherein an input to the voltage regulator is between substantially 4 volts and substantially 25 volts DC, and wherein the predetermined level is substantially 3.3 volts.

7. The microcontroller of claim 1 , wherein the battery management system further comprises:

a first analog to digital converter (ADC) to provide an instantaneous current output value and an accumulate current output value.

8. The microcontroller of claim 7 , wherein if the instantaneous current output value is greater than a programmable threshold current, then the first ADC generates an interrupt to the microcontroller to allow for low power operation.

9. The microcontroller of claim 7 , wherein the battery management system further comprises:

a second analog to digital converter (ADC) to measure a cell voltage, wherein the first ADC and the second ADC are to provide continuous voltage and current monitoring of each cell of the plurality of cells.

10. The microcontroller of claim 9 , wherein the battery management system includes an on-chip voltage reference coupled to the first ADC and the second ADC to provide an accurate reference voltage to the first ADC and the second ADC.

11. The microcontroller of claim 2 , wherein the battery protection circuit further comprises a first circuit portion to protect the battery from an overcurrent condition or a short circuit condition by monitoring a charge current and a discharge current from the battery.

12. The microcontroller of claim 11 , wherein the battery protection circuitry further comprises a second circuit portion to protect the battery from discharge deeper than a programmable deep undervoltage protection level.

13. A microcontroller comprising:

a processor system including a data bus;

a high voltage battery interface coupled to the processor system, wherein a battery to be coupled to the battery interface comprises a plurality of cells, wherein the high voltage battery interface includes a plurality of inputs to the microcontroller capable of operating in a range of 4 volts to 25 volts; and

a battery management system to monitor the battery and to manage the battery based upon monitoring of the battery, wherein the battery management system comprises:

a battery protection circuit to detect at least one illegal condition on the battery and to protect the battery from the at least one illegal condition;

a first analog to digital converter (ADC) to provide an instantaneous current output value and an accumulate current output value, wherein if the instantaneous current output value is greater than a programmable threshold current, then the first ADC generates an interrupt to the microcontroller to allow for low power operation;

a second analog to digital converter (ADC) to measure a cell voltage, wherein the first ADC and the second ADC are to provide continuous voltage and current monitoring of each cell of the plurality of cells;

an on-chip voltage reference coupled to the first ADC and second the ADC to provide an accurate reference voltage to the first ADC and the second ADC; and

a control system to control charging and discharging of the battery,

wherein the control system includes a plurality of cell-balancing FETs coupled to the plurality of cells and to the data bus, wherein there is one cell-balancing FET coupled to each of the plurality of cells, and wherein each cell balancing FET of the plurality of cell-balancing FETs is directly controlled by reprogrammable application software via a control register coupled to the data bus; and

wherein the microcontroller is a single chip.

14. The microcontroller of claim 13 , wherein the at least one illegal condition comprises at least one of: a deep under-voltage during discharging, a short circuit during discharging, and an over-current during charging or discharging.

15. The microcontroller of claim 13 , wherein the processor system further comprises:

a central processing unit (CPU).

16. The microcontroller of claim 13 , wherein the battery management system further comprises:

a voltage regulator adapted to be coupled to the battery via the high voltage battery interface, wherein the voltage regulator is to regulate a supply voltage to the microcontroller at a predetermined level.

17. The microcontroller of claim 16 , wherein an input to the voltage regulator is between substantially 4 volts and substantially 25 volts DC, and wherein the predetermined level is substantially 3.3 volts.

18. The microcontroller of claim 13 , wherein the battery management system includes an on-chip voltage reference coupled to the first ADC and the second ADC to provide an accurate reference voltage to the first ADC and the second ADC.

19. The microcontroller of claim 13 , wherein the battery protection circuit further comprises a first circuit portion to protect the battery from an overcurrent condition or a short circuit condition by monitoring a charge current and a discharge current from the battery.

20. The microcontroller of claim 19 , wherein the battery protection circuitry further comprises a second circuit portion to protect the battery from discharge deeper than a programmable deep undervoltage protection level.

21. The microcontroller of claim 13 , wherein the high voltage battery interface includes a high voltage input to at least one of the first ADC and the second ADC, wherein the high voltage input is configured to operate up to substantially 25 volts.

Assignments (17)
RELEASE OF SECURITY INTEREST Recorded Mar 14, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 060894/0437 →
RELEASE OF SECURITY INTEREST Recorded Mar 11, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059363/0001 →
RELEASE OF SECURITY INTEREST Recorded Mar 10, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059863/0400 →
RELEASE OF SECURITY INTEREST Recorded Mar 9, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059358/0001 →
RELEASE OF SECURITY INTEREST Recorded Feb 28, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: ATMEL CORPORATION
Reel/Frame 059262/0105 →
RELEASE OF SECURITY INTEREST Recorded Feb 25, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059333/0222 →
SECURITY INTEREST Recorded Jun 4, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 057935/0474 →
SECURITY INTEREST Recorded Dec 24, 2020
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 055671/0612 →
SECURITY INTEREST Recorded Jun 5, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 053468/0705 →
RELEASE OF SECURITY INTEREST Recorded May 30, 2020
From: JPMORGAN CHASE BANK, N.A, AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 053466/0011 →
SECURITY INTEREST Recorded Apr 24, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 053311/0305 →
SECURITY INTEREST Recorded Sep 18, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 047103/0206 →
SECURITY INTEREST Recorded Jun 25, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 046426/0001 →
SECURITY INTEREST Recorded Feb 10, 2017
From: ATMEL CORPORATION
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 041715/0747 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT COLLATERAL Recorded Apr 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: ATMEL CORPORATION
Reel/Frame 038376/0001 →
PATENT SECURITY AGREEMENT Recorded Jan 3, 2014
From: ATMEL CORPORATION
To: MORGAN STANLEY SENIOR FUNDING, INC. AS ADMINISTRATIVE AGENT
Reel/Frame 031912/0173 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 17, 2006
From: GANGSTO, GUNNAR; AAS, ARNE; SORASEN, RUNAR
To: ATMEL CORPORATION
Reel/Frame 017770/0400 →
Continuity (1)
Related Publication 20060170398A1 · Aug 3, 2006