Strained-silicon CMOS device and method
View Patent ↗The present invention provides a semiconductor device and a method of forming thereof, in which a uniaxial strain is produced in the device channel of the semiconductor device. The uniaxial strain may be in tension or in compression and is in a direction parallel to the device channel. The uniaxial strain can be produced in a biaxially strained substrate surface by strain inducing liners, strain inducing wells or a combination thereof. The uniaxial strain may be produced in a relaxed substrate by the combination of strain inducing wells and a strain inducing liner. The present invention also provides a means for increasing biaxial strain with strain inducing isolation regions. The present invention further provides CMOS devices in which the device regions of the CMOS substrate may be independently processed to provide uniaxially strained semiconducting surfaces in compression or tension.
1. A semiconducting device comprising:
a semiconducting substrate, wherein said semiconducting substrate comprises a biaxial tensile strain induced by an underlying strain inducing layer comprising SiGe having Ge present in a concentration ranging from about 5% to about 50%;
a source region and a drain region located within said semiconducting substrate;
at least one gate region including a gate conductor atop a device channel portion of said semiconducting substrate, said device channel portion separating said source and drain regions;
a sidewall spacer abutting each gate region;
strain inducing wells adjacent said at least one gate region, said strain inducing wells comprising silicon doped with carbon or silicon germanium doped with carbon, wherein each of said strain inducing wells is embedded in and surrounded by said source region or said drain region and comprises a different material than said source and drain regions and top surfaces of said strain inducing wells contact bottom surfaces of said sidewall spacer, wherein at least some portion of said strain inducing wells is located in an undercut area directly beneath said sidewall spacer; and
a strain inducing liner positioned directly on said straining inducing wells and top surfaces of said source region and said drain region, wherein said strain inducing liner comprises an oxide, a doped oxide, a nitride, Al 2 O 3 , HfO 2 , ZrO 2 , or HfSiO, wherein said strain inducing liner and said strain inducing wells in said semiconducting substrate introduce a uniaxial strain in tension in the device channel portion in a direction parallel to a length of said device channel portion.