Lithography for printing constant line width features
View Patent ↗An anisotropic wet etch of a semiconductor layer generates facets joined by a ridge running along the center of a pattern in a dielectric hardmask layer on the semiconductor layer. The dielectric hardmask layer is removed and a conformal masking material layer is deposited. Angled ion implantation of Ge, B, Ga, In, As, P, Sb, or inert atoms is performed parallel to each of the two facets joined by the ridge causing damage to implanted portions of the masking material layer, which are removed selective to undamaged portions of the masking material layer along the ridge and having a constant width. The semiconductor layer and a dielectric oxide layer underneath are etched selective to the remaining portions of the dielectric nitride. Employing remaining portions of the dielectric oxide layer as an etch mask, the gate conductor layer is patterned to form gate conductor lines having a constant width.
1. A method of forming a semiconductor structure comprising:
forming a stack, from bottom to top, of a gate dielectric layer, a gate conductor layer, a dielectric oxide layer, and a semiconductor layer on a semiconductor substrate;
forming crystallographic facets joined by a ridge in said semiconductor layer by an anisotropic wet etch;
forming a masking material layer on said crystallographic facets;
forming implantation-damaged masking material portions by implanting Ge, B, Ga, In, As, P, Sb, or inert atoms into said masking material layer, whereby a portion of said masking material layer is not implanted by said Ge, B, Ga, In, As, P, Sb, or inert atoms to form an undamaged masking material portion;
removing said implantation-damaged masking material portions selective to said undamaged masking material portion; and
etching said semiconductor layer and said dielectric oxide layer employing said undamaged masking material portion as an etch mask.
2. The method of claim 1 , wherein said masking material layer comprises a dielectric nitride or an undoped silicon containing semiconductor material.
3. The method of claim 2 , wherein said implantation-damaged masking material portion comprises a dielectric nitride and at least one of Ge or inert atoms, wherein said implantation-damaged masking material portion has more structural damage than said undamaged masking material portion.
4. The method of claim 2 , wherein said implantation-damaged masking material portion comprises an undoped silicon-containing-semiconductor material and at least one of Ge, B, Ga, In, As, P, and Sb, wherein said undamaged masking material portion is substantially undoped.
5. The method of claim 1 , wherein said Ge, B, Ga, In, As, P, Sb, or inert atoms are implanted at a first angle that is substantially parallel to one of said crystallographic facets adjoined to said ridge and at a second angle that is substantially parallel to another of said crystallographic facets adjoined to said ridge.
6. The method of claim 1 , wherein a vertical cross-sectional area of said undamaged masking material portion is a rhombus.
7. The method of claim 1 , further comprising etching said gate conductor layer employing at least one of said undamaged masking material portion and a remaining portion of said dielectric oxide layer as an etch mask.
8. The method of claim 7 , further comprising forming a field effect transistor employing a remaining portion of said gate conductor layer as a gate conductor of said field effect transistor.
9. The method of claim 1 , further comprising:
forming a dielectric hardmask layer directly on said semiconductor layer; and
forming an opening in said dielectric hardmask layer, wherein said crystallographic facets are formed underneath said opening.
10. The method of claim 9 , wherein an edge of each of said crystallographic facets is directly adjoined to an edge of said opening in said dielectric hardmask layer.
11. The method of claim 9 , further comprising:
applying a photoresist on said dielectric hardmask layer;
lithographically patterning said photoresist; and
etching an exposed portion of said dielectric hardmask layer to from said opening employing said photoresist as an etch mask.
12. The method of claim 1 , wherein surface orientations of said crystallographic facets are one of {100} orientations, {110} orientations, {111} orientations, {211} orientations, {221} orientations, and {311} orientations.
13. The method of claim 1 , wherein said semiconductor layer is formed by bonding another semiconductor substrate containing a hydrogen implanted layer to said dielectric oxide layer and cleaving said another semiconductor substrate along said hydrogen implanted layer, wherein a portion of said another semiconductor substrate between said dielectric oxide layer and said hydrogen implanted layer constitutes said semiconductor layer.
14. A method of forming a semiconductor structure comprising:
forming a stack, from bottom to top, of a gate dielectric layer, a gate conductor layer, a dielectric material layer, and a semiconductor layer on a semiconductor substrate;
forming crystallographic facets joined by a ridge in said semiconductor layer by an anisotropic wet etch;
forming at least one undamaged masking material portion that is not damaged by ion implantation directly on said ridge, wherein said undamaged masking material portion has a vertical cross-sectional area of a rhombus; and
patterning said semiconductor layer and said dielectric material layer employing said undamaged masking material portion as an etch mask.
15. The method of claim 14 , further comprising:
transferring a pattern of said at least one undamaged masking material portion into said gate conductor layer to form at least one gate conductor line; and
forming a field effect transistor, wherein one of said at least one gate electrode line is a gate electrode of said field effect transistor.