Heterojunction device comprising a semiconductor and a resistivity-switching oxide or nitride
In the present invention a metal oxide or nitride compound which is a wide-band-gap semiconductor abuts a silicon, germanium, or alloy of silicon and/or germanium of the opposite conductivity type to form a p-n heterojunction. This p-n heterojunction can be used to advantage in various devices. In preferred embodiments, one terminal of a vertically oriented p-i-n heterojunction diode is a metal oxide or nitride layer, while the rest of the diode is formed of a silicon or silicon-germanium resistor; for example a diode may include a heavily doped n-type silicon region, an intrinsic silicon region, and a nickel oxide layer serving as the p-type terminal. Many of these metal oxides and nitrides exhibit resistivity-switching behavior, and such a heterojunction diode can be used in a nonvolatile memory cell, for example in a monolithic three dimensional memory array.
1. A memory cell comprising a heterojunction diode comprising:
a semiconductor element comprising:
a first semiconductor layer of heavily doped silicon, germanium, silicon-germanium, or an alloy thereof of a first conductivity type; and
a second semiconductor layer of silicon, germanium, silicon-germanium, or an alloy thereof, the second semiconductor layer above and in contact with the first semiconductor layer, wherein the second semiconductor layer is intrinsic or lightly doped to the first conductivity type; and
a switching element comprising a layer of a conductive binary metal oxide or nitride compound above and in contact with the second semiconductor layer, wherein a p-n junction is formed between the second semiconductor layer and the layer of the conductive binary metal oxide or nitride compound,
wherein the switching element has a first polarity and the second semiconductor layer has a second polarity opposite the first polarity.
2. The memory cell of claim 1 wherein the first and second semiconductor layers are polycrystalline.
3. The memory cell of claim 1 wherein the conductive binary metal oxide or nitride has a resistivity less than one megaOhm-cm.
4. The memory cell of claim 1 wherein the binary metal oxide or nitride compound is selected from the group consisting of Ni x O y , Nb x O y , Ti x O y , Hf x O y , Al x O y , Mg x O y , Co x O y , Cr x O y , V x O y , Zn x O y , Zr x O y , B x N y , Al x N y .
5. The semiconductor device of claim 4 wherein the binary metal oxide or nitride compound is NiO and the first conductivity type is n-type.
6. The memory cell of claim 1 , wherein the binary metal oxide or nitride compound is selected from the group consisting of NiO, Nb 2 O 5 , TiO 2 , HfO 2 , Al 2 O 3 , MgO x , CoO, CrO 2 , VO, ZnO, ZrO, BN, and AlN.
7. The memory cell of claim 1 , wherein the binary metal oxide or nitride compound is switchable between at least a stable high-resistivity state and a stable low-resistivity state, wherein the difference in resistivity between the high-resistivity state and the low-resistivity state is at least a factor of three.
8. The heterojunction device of claim 1 , wherein the heterojunction diode is a p-i-n diode.
9. The memory cell of claim 1 , wherein the heterojunction diode is vertically oriented.
10. The memory cell of claim 1 , wherein the semiconductor element is in the form of a pillar.
11. The heterojunction device of claim 1 , wherein at least a portion of the semiconductor element is doped with an n-type dopant.
12. The memory cell of claim 1 , wherein at least a portion of the semiconductor element is doped with a p-type dopant.
13. The memory cell of claim 1 , wherein the resistivity of the binary metal oxide or nitride compound is less than about 1 kiloOhm-cm.
14. The memory cell of claim 1 , wherein the resistivity of the binary metal oxide or nitride compound is less than about 1 microOhm-cm.