Mechanism for using performance counters to identify reasons and delay times for instructions that are stalled during retirement

1. A method comprising:

detecting a first reason which prevents exit of an entry from an instruction retirement queue;

incrementing a first count corresponding to the first reason, wherein the first count is incremented while the first reason prevents exit of the entry from the instruction retirement queue;

determining a first point in time when said first reason no longer prevents exit of the entry from the instruction retirement queue;

detecting a second reason which prevents exit of the entry from the instruction retirement queue, wherein the second reason came into existence prior to said first point in time; and

incrementing a second count corresponding to the second reason, wherein incrementing the second count begins at the first point in time.

2. The method as recited in claim 1 , wherein the first count represents a contribution of the first reason for a delay of exit of the entry from the instruction retirement queue, and the second count represents a contribution of the second reason for the delay.

3. The method as recited in claim 2 , further comprising assigning highest priority to an oldest entry in said instruction retirement queue.

4. The method as recited in claim 3 , further comprising operating pipeline coupled to the instruction retirement queue in a superscalar microarchitecture comprising out-of-order and parallel execution of operations of a processor.

5. The method as recited in claim 4 , further comprising operating said instruction retirement queue as a superscalar reorder buffer that retires said operations in-order.

6. The method as recited in claim 1 , wherein said first reason and said second reason are selected from one of a branch misprediction, an i-TLB miss, and i-cache miss, a long dispatch, a dependency between instructions, a d-TLB miss, or d-cache miss.

7. A system comprising:

an instruction pipeline;

an instruction retirement queue; and

a performance monitor coupled to the instruction pipeline and the instruction retirement queue, wherein the performance monitor is configured to:

detect a first reason which prevents exit of an entry from the instruction retirement queue;

increment a first count corresponding to the first reason, wherein the first count is incremented while the first reason prevents exit of the entry from the instruction retirement queue;

determine a first point in time when said first reason no longer prevents exit of the entry from the instruction retirement queue;

detect a second reason which prevents exit of the entry from the instruction retirement queue, wherein the second reason came into existence prior to said first point in time; and

increment a second count corresponding to the second reason, wherein incrementing the second count begins at the first point in time.

8. The system as recited in claim 7 , wherein the first count represents a contribution of the first reason for a delay of exit of the entry from the instruction retirement queue, and the second count represents a contribution of the second reason for the delay.

9. The system as recited in claim 8 , wherein an entry in said instruction retirement queue is configured to store an entity being processed by the instruction pipeline and an associated status of the entity.

10. The system as recited in claim 9 , wherein the instruction retirement queue is configured to assign highest priority to the oldest entry.

11. The system as recited in claim 7 , wherein the instruction pipeline is configured to operate in a superscalar microarchitecture comprising out-of-order and parallel execution of instructions of a processor.

12. The system as recited in claim 11 , wherein the instruction retirement queue is further configured to operate as a superscalar reorder buffer.

13. The system as recited in claim 7 , wherein said first reason and said second reason are selected from one of a branch misprediction, an i-TLB miss, and i-cache miss, a long dispatch, a dependency between instructions, a d-TLB miss, or d-cache miss.

14. The system as recited in claim 13 , wherein the performance monitor is configured to use existing hardware resources in the pipeline to determine IPC loss in the pipeline.

15. An performance monitor comprising:

an interface configured to communicate with a pipeline including an instruction retirement queue;

a first counter;

a second counter; and

a control unit, wherein the control unit is configured to:

detect a first reason which prevents exit of an entry from the instruction retirement queue;

increment a first count corresponding to the first reason, wherein the first count is incremented while the first reason prevents exit of the entry from the instruction retirement queue;

determine a first point in time when said first reason no longer prevents exit of the entry from the instruction retirement queue;

detect a second reason which prevents exit of the entry from the instruction retirement queue, wherein the second reason came into existence prior to said first point in time; and

increment a second count corresponding to the second reason, wherein incrementing the second count begins at the first point in time.

16. The performance monitor as recited in claim 15 , wherein the control unit is further configured to detect a condition of an unsuccessful exit from said instruction retirement queue of only an entry which has a highest priority according to said instruction retirement queue.

17. The performance monitor as recited in claim 15 , wherein the control unit is further configured to detect said first and second reason to be one of a branch misprediction, i-TLB miss, i-cache miss, a long dispatch, a dependency between instructions, or a d-TLB or d-cache miss.

18. The performance monitor as recited in claim 15 , wherein the instruction retirement queue comprises a reorder buffer.