Inter-stage matching network to enhance common mode stability
A two stage amplifier with an inter-stage matching network constituted of a first and a second transistor forming a differential first stage, a third and a fourth transistor forming a differential second stage, an on-chip connection path connecting the emitters of the first and second transistor to the emitters of the third and fourth transistors, a first transformation network and a second transformation network. A collector of the first transistor is operatively connected to a base of the third transistor by the first transformation network and a collector of the second transistor is operatively connected to a base of the fourth transistor by the second transformation network. At least one resistor is provided in the on-chip connection path to stabilize the input of the third and fourth transistors.
1. An amplifier comprising:
a. a first stage differential amplifier having
i. at least one first transistor, and
ii. at least one second transistor,
wherein said at least one first transistor and said at least one second transistor are arranged to form said first stage differential amplifier with a first stage common node;
b. a second stage differential amplifier having
i. at least one third transistor, and
ii. at least one fourth transistor;
wherein said at least one third transistor and said at least one fourth transistor are arranged to form said second stage differential amplifier with a second stage common node;
c. an on-chip connection path arranged to connect the first stage common node to the second stage common node;
d. a first transformation network comprising a first shunt component and a second shunt component, said first shunt component closer to said second stage than said second shunt component, an end of said first shunt component connected to a first node of said on-chip connection path and an end of said second shunt component connected to a second node of said on-chip connection path; and
e. a second transformation network comprising a third shunt component and a fourth shunt component, said third shunt component closer to said second stage than said fourth shunt component, an end of said third shunt component connected to the first node of said on-chip connection path, and an end of said fourth shunt component connected to the second node of said on-chip connection path,
wherein
a first output of said first differential stage, associated with said at least one first transistor, is operatively connected to a first input of said second differential stage, associated with said third transistor, by said first transformation network,
a second output of said first differential stage, associated with said at least one second transistor, is operatively connected to a second input of said second differential stage, associated with said fourth transistor, by said second transformation network, and
wherein said on-chip connection path comprises a first resistor inserted between the second stage common node and the first node of the on-chip connection.
2. The amplifier of claim 1 , wherein a first input of said first stage differential amplifier, associated with said at least one first transistor, and a second input of said first stage differential amplifier, associated with said at least one second transistor, are operatively coupled to an input of said amplifier.
3. The amplifier of claim 2 , wherein a first output of said second stage differential amplifier, associated with said at least one third transistor, and a second output of said second stage differential amplifier, associated with said at least one fourth transistor, are operatively coupled to an output of said amplifier.
4. The amplifier of claim 1 , wherein
a. said at least one first transistor further comprises a plurality of transistors connected in parallel;
b. said at least one second transistor further comprises a plurality of transistors connected in parallel;
c. said at least one third transistor further comprises a plurality of transistors connected in parallel; and
d. said at least one fourth transistor further comprises a plurality of transistors connected in parallel.
5. The amplifier of claim 1 , further comprising:
a first wirebond arranged to connect the second stage common node to ground.
6. The amplifier of claim 5 , further comprising a second wirebond arranged to connect the first stage common node to ground.
7. The amplifier of claim 6 , wherein said on-chip connection path further comprises a second resistor inserted between the first node and the second node of the on-chip connection path.
8. The amplifier of claim 1 , wherein each of said first transformation network and said second transformation network further comprises an additional shunt path comprising a series connected inductor and capacitor, one end of the additional shunt path of each of said first transformation network and said second transformation network connected to the second node of said on-chip connection path.
9. The amplifier of claim 1 , wherein said at least one first transistor and said at least one second transistor are constituted of bipolar transistors.
10. The amplifier of claim 1 , wherein said at least one third transistor and said at least one fourth transistor are constituted of bipolar transistors.
11. The amplifier of claim 1 , wherein said at least one first transistor and said at least one second transistor are constituted of field effect transistors.
12. The amplifier of claim 1 , wherein said at least one third transistor and said at least one fourth transistor are constituted of field effect transistors.
13. The amplifier of claim 1 , wherein at least one of said first stage differential amplifier and said second stage differential amplifier are constituted of three terminal transconductance amplifier devices.