IP Library Granted Patent US 7,956,449
Granted Patent B2
US 7,956,449 · App. 12/146,135 · Granted Jun 7, 2011

Stacked integrated circuit package system

Assignee: STATS Chippac Ltd.
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Quick Facts
Patent No.
US 7,956,449
App. No.
12/146,135
Granted
Jun 7, 2011
Kind
B2
Abstract

A stacked integrated circuit package system includes: forming a recessed integrated circuit package system having a first encapsulation over a first integrated circuit and an interior cavity in the first encapsulation; forming a mountable integrated circuit package system having a second integrated circuit over a carrier; and mounting the recessed integrated circuit package system over the mountable integrated circuit package system with the second integrated circuit within the interior cavity and the first integrated circuit coupled with the carrier.

Claims (46)

1. A method for manufacturing a stacked integrated circuit package system comprising:

forming a recessed integrated circuit package system having a first encapsulation over a first integrated circuit, an interior cavity in the first encapsulation, a mounting structure, a conductive site comprised of substantially the same material as the mounting structure. and the first integrated circuit connected with the conductive site over a peripheral cavity of the first encapsulation:

forming a mountable integrated circuit package system having a second integrated circuit over a carrier; and

mounting the recessed integrated circuit package system over the mountable integrated circuit package system with the second integrated circuit within the interior cavity and the first integrated circuit coupled with the carrier.

2. The method as claimed in claim 1 wherein forming the recessed integrated circuit package system includes:

forming the mounting structure and the conductive site comprised of substantially the same material as the mounting structure; and

mounting the first integrated circuit over the mounting structure and over the interior cavity.

3. The method as claimed in claim 1 wherein:

forming the mountable integrated circuit package system includes forming a second encapsulation over the second integrated circuit; and

mounting the recessed integrated circuit package system over the mountable integrated circuit package system includes fitting the second encapsulation within the interior cavity.

4. The method as claimed in claim 1 wherein:

forming the recessed integrated circuit package system includes connecting the first integrated circuit with the conductive site over the peripheral cavity of the first encapsulation;

forming the mountable integrated circuit package system includes forming a stacking interconnect over the carrier; and

mounting the recessed integrated circuit package system over the mountable integrated circuit package system includes connecting the stacking interconnect within the peripheral cavity.

5. A method for manufacturing a stacked integrated circuit package system comprising:

forming a recessed integrated circuit package system having a first encapsulation over a first integrated circuit, an interior cavity in the first encapsulation, and the first encapsulation having a peripheral cavity with a conductive site exposed and a wall of the peripheral cavity in a non-vertical configuration includes:

forming a mounting structure and the conductive site comprised of substantially the same material as the mounting structure,

mounting the first integrated circuit over the mounting structure and over the interior cavity, and

connecting the first integrated circuit and the conductive site;

forming a mountable integrated circuit package system having a second integrated circuit over a carrier; and

mounting the recessed integrated circuit package system over the mountable integrated circuit package system with the second integrated circuit within the interior cavity and the first integrated circuit coupled with the carrier.

6. The method as claimed in claim 5 wherein mounting the recessed integrated circuit package system over the mountable integrated circuit package system includes connecting the conductive site and the carrier.

7. The method as claimed in claim 5 wherein forming the mountable integrated circuit package system having the second integrated circuit includes mounting a flip chip over the carrier.

8. The method as claimed in claim 5 further comprising attaching an external interconnect below and to the carrier.

9. A stacked integrated circuit package system comprising:

a recessed integrated circuit package system having a first encapsulation over a first integrated circuit, an interior cavity in the first encapsulation, a mounting structure exposed by the first encapsulation. a conductive site exposed by the first encapsulation and comprised of substantially the same material as the mounting structure, and the first integrated circuit connected with the conductive site over a peripheral cavity of the first encapsulation: and

a mountable integrated circuit package system having a second integrated circuit over a carrier with the recessed integrated circuit package system thereover with the second integrated circuit within the interior cavity and the first integrated circuit coupled with the carrier.

10. The system as claimed in claim 9 wherein the recessed integrated circuit package system includes:

the mounting structure exposed by the first encapsulation;

the conductive site exposed by the first encapsulation and comprised of substantially the same material as the mounting structure; and

the first integrated circuit over the mounting structure and over the interior cavity.

11. The system as claimed in claim 9 wherein:

the mountable integrated circuit package system includes a second encapsulation over the second integrated circuit; and

the recessed integrated circuit package system over the mountable integrated circuit package system includes the second encapsulation within the interior cavity.

12. The system as claimed in claim 9 wherein:

the recessed integrated circuit package system includes the first integrated circuit connected with the conductive site over the peripheral cavity of the first encapsulation;

the mountable integrated circuit package system includes a stacking interconnect over the carrier; and

the recessed integrated circuit package system mounted over the mountable integrated circuit package system includes the stacking interconnect within the peripheral cavity.

13. The system as claimed in claim 9 wherein the recessed integrated circuit package system includes:

the mounting structure exposed by the first encapsulation;

the conductive site exposed by the first encapsulation and comprised of substantially the same material as the mounting structure; and

the first integrated circuit over the mounting structure and over the interior cavity, and connected with the conductive site.

14. The system as claimed in claim 13 wherein the recessed integrated circuit package system over the mountable integrated circuit package system includes the conductive site connected with the carrier.

15. The system as claimed in claim 13 wherein the recessed integrated circuit package system includes the first encapsulation having the peripheral cavity with the conductive site exposed and a wall of the peripheral cavity in a non-vertical configuration.

16. The system as claimed in claim 13 wherein the mountable integrated circuit package system having the second integrated circuit includes a flip chip over the carrier.

17. The system as claimed in claim 13 further comprising an external interconnect below and attached to the carrier.

Assignments (8)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 3, 2025
From: STATS CHIPPAC PTE. LTD.
To: STATS CHIPPAC MANAGEMENT PTE. LTD.
Reel/Frame 072788/0917 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE'S NAME ON COVER SHEET FROM STATS CHIPPAC PTE. LTE. TO STATS CHIPPAC PTE. LTD. PREVIOUSLY RECORDED ON REEL 064783 FRAME 0896. ASSIGNOR(S) HEREBY CONFIRMS THE CORRECTIVE CHANGE OF NAME. Recorded Sep 22, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 065015/0917 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE'S NAME ON COVERSHEET FROM STATS CHIPPAC PTE. LTE. TO STATS CHIPPAC PTE. LTD. PREVIOUSLY RECORDED ON REEL 038378 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE CHANGE OF NAME. Recorded Sep 14, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 064962/0123 →
CORRECT ERROR IN ASSIGNMENT NAME FROM STATS CHIPPAC PTE. LTE. TO STATS CHIPPAC PTE. LTD. (REEL: 038378 FRAME: 0292) Recorded Aug 30, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE.LTE.
Reel/Frame 064783/0896 →
RELEASE OF SECURITY INTEREST Recorded Jun 11, 2020
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 052907/0650 →
CHANGE OF NAME Recorded Apr 7, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0292 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 3, 2008
From: LEE, KYUNGHOON; KIM, OH HAN
To: STATS CHIPPAC LTD.
Reel/Frame 021195/0789 →
Continuity (1)
Related Publication 20090321907A1 · Dec 31, 2009