Method of forming an embedded barrier layer for protection from chemical mechanical polishing process
View Patent ↗A semiconductor interconnect structure and method providing an embedded barrier layer to prevent damage to the dielectric material during or after Chemical Mechanical Polishing. The method employs a combination of an embedded film, etchback, using either selective CoWP or a conformal cap such as a SiCNH film, to protect the dielectric material from the CMP process as well as subsequent etch, clean and deposition steps of the next interconnect level.
1. A method of making an electronic device comprising the steps of:
providing a first diffusion barrier layer;
providing a first dielectric layer on said first diffusion barrier layer;
providing a hardmask layer on said first dielectric layer;
providing an oxide layer on said hardmask layer;
forming openings in said oxide, hardmask and first dielectric layers;
providing a liner layer;
providing a metal layer;
removing a portion of said metal layer and said liner layer, wherein a top surface of a remaining portion of said metal layer is coplanar with a top surface of a remaining portion of said liner layer;
selectively etching said oxide layer, wherein said top surface of said remaining portion of said metal layer and said top surface of said remaining portion of said liner layer protrude above a top surface of said hardmask layer;
forming a second diffusion barrier layer contiguously on said hardmask layer and said metal layer, and
providing a second dielectric layer on said second diffusion barrier layer.
2. The method of claim 1 wherein said selective etch is a dilute HF etch.
3. The method of claim 1 wherein said selective etch is a selective dry plasma etch.
4. The method of claim 1 wherein said second diffusion barrier layer in an SiCNH layer.
5. The method of claim 1 wherein said hardmask layer is SiCOH.
6. The method of claim 1 wherein said first and second dielectric layers are ULK dielectrics.
7. The method of claim 1 wherein said metal layer is a plated copper layer.
8. The method of claim 1 wherein said metal layer and oxide layer removal is a CMP removal.
9. A method of making an electronic device comprising the steps of:
providing a first diffusion barrier layer;
providing a first dielectric layer on said first diffusion barrier layer;
providing a hardmask layer on said first dielectric layer;
providing an oxide layer on said hardmask layer;
forming openings in said oxide, hardmask and first dielectric layers;
providing a liner layer;
providing a metal layer;
removing a portion of said metal layer and said liner layer, wherein a top surface of a remaining portion of said metal layer is coplanar with a top surface of a remaining portion of said liner layer;
selectively etching said oxide layer, wherein said top surface of said remaining portion of said metal layer and said top surface of said remaining portion of said liner layer protrude above a top surface of said hardmask layer;
forming a second diffusion barrier layer selectively on said metal layer, and providing a second dielectric layer on said second diffusion barrier layer and said hardmask layer.
10. The method of claim 9 wherein said selective etch is a dilute HF etch.
11. The method of claim 9 wherein said selective etch is a selective dry plasma etch.
12. The method of claim 9 wherein said second diffusion barrier layer in a CoWP layer.
13. The method of claim 9 wherein said hardmask layer is SiCOH.
14. The method of claim 9 wherein said first and second dielectric layers are ULK dielectrics.
15. The method of claim 9 wherein said metal layer is a plated copper layer.
16. The method of claim 9 wherein said metal layer and oxide layer removal is a CMP removal.