IP Library Granted Patent US 8,003,468
Granted Patent B2
US 8,003,468 · App. 12/195,324 · Granted Aug 23, 2011

Separation methods for semiconductor charge accumulation layers and structures thereof

Assignee: Spansion LLC
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Quick Facts
Patent No.
US 8,003,468
App. No.
12/195,324
Granted
Aug 23, 2011
Kind
B2
Abstract

Devices and methods for isolating adjacent charge accumulation layers in a semiconductor device are disclosed. In one embodiment, a semiconductor device comprises a bit line formed in a semiconductor substrate, a charge accumulation layer formed on the semiconductor substrate, a word line formed on the charge accumulation layer across the bit line, and a channel region formed in the semiconductor substrate below the word line and between the bit line and its adjacent bit line. For the semiconductor device, the charge accumulation layer is formed above the channel region in a widthwise direction of the word line, and a width of the word line is set to be narrower than a distance between an end of the channel region and a central part of the channel region in a lengthwise direction of the word line.

Claims (36)

1. A method for manufacturing a semiconductor device, the method comprising:

forming a bit line in a semiconductor substrate;

forming an oxide nitride oxide (ONO) film which includes a charge accumulation layer on the semiconductor substrate;

forming a word line on the ONO film and across the bit line;

forming a hole in the ONO film between the word line and its adjacent word line and between the bit line and an adjacent bit line; and

isotropically etching the charge accumulation layer via the hole.

2. The method of claim 1 , wherein the forming the bit line comprises:

implanting an arsenic ion in the semiconductor substrate; and

heat treating the semiconductor substrate.

3. The method of claim 1 , wherein the forming the ONO film comprises:

forming a tunnel insulating film on the semiconductor substrate;

forming the charge accumulation layer on the tunnel insulating film; and

forming a top insulating film on the charge accumulation layer.

4. The method of claim 3 , wherein the forming the hole comprises:

coating a photoresist on the ONO film and the word line;

forming an opening at a central part of the photoresist using a resist-shrink process; and

dry-etching the central part of the photoresist to form the hole in the ONO film.

5. The method of claim 4 , wherein the hole is formed at the central part of the photoresist and the top insulating film.

6. The method of claim 1 , wherein the etching the charge accumulation layer comprises applying a photosphoric acid into the hole to form a hollow section by removing outer edges of the charge accumulation layer.

7. The method of claim 6 , wherein the hollow section isolates the bit line from its adjacent bit line.

8. The method of claim 6 , further comprising filling the hollow section with a dielectric material.

9. The method of claim 1 , further comprising forming a channel region in the semiconductor substrate below the word line and between the bit line and the adjacent bit line.

10. The method of claim 9 , wherein the charge accumulation layer is formed above the channel region in a widthwise direction of the word line, and wherein a width of the word line is set to be narrower than a distance between an end of the channel region and a central part of the channel region in a lengthwise direction of the word line.

11. A method for manufacturing a semiconductor device, the method comprising:

forming a bit line in a semiconductor substrate;

forming an oxide nitride oxide (ONO) film which includes a charge accumulation layer on the semiconductor substrate;

forming a word line on the ONO film and across the bit line;

forming a hole in the ONO film between the word line and its adjacent word line and between the bit line and its adjacent bit line; and

isotropically etching the charge accumulation layer via the hole by applying a phosphoric acid to the hole to form a hollow section by removing outer edges of the charge accumulation layer, wherein the hollow section is formed such that the bit line is connected to an adjacent bit line via a narrow path in a lengthwise direction of the word line.

12. The method of claim 11 , wherein the forming the hole comprises:

coating a photoresist on the ONO film and the word line;

forming an opening at the central part of the photoresist using a resist-shrink process; and

dry-etching the central part of the photoresist to form the hole in the ONO film.

13. The method of claim 12 , wherein the hole is formed at the central part of the photoresist and the top insulating film.

14. The method of claim 13 , wherein the etching the charge accumulation layer comprises phosphoric acid to the hole to remove outer edges of the charge accumulation layer.

15. The method of claim 11 , wherein the charge accumulation layer is formed above the channel region in a widthwise direction of the word line, and wherein a width of the word line is set to be narrower than a distance between an end of the channel region and a central part of the channel region in a lengthwise direction of the word line.

Assignments (9)
CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST. Recorded Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
RELEASE OF SECURITY INTEREST Recorded Dec 19, 2019
From: MUFG UNION BANK, N.A.
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 051334/0633 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 11, 2019
From: CYPRESS SEMICONDUCTOR CORPORATION
To: LONGITUDE FLASH MEMORY SOLUTIONS LIMITED
Reel/Frame 051251/0787 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN INTELLECTUAL PROPERTY Recorded Oct 28, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: MUFG UNION BANK, N.A.
Reel/Frame 050896/0366 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 2, 2015
From: SPANSION, LLC
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 036050/0514 →
SECURITY INTEREST Recorded Mar 21, 2015
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 035240/0429 →
RELEASE OF SECURITY INTEREST Recorded Mar 13, 2015
From: BARCLAYS BANK PLC
To: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY LLC
Reel/Frame 035201/0159 →
SECURITY AGREEMENT Recorded Jun 4, 2010
From: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY INC.; SPANSION TECHNOLOGY LLC
To: BARCLAYS BANK PLC
Reel/Frame 024522/0338 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 25, 2008
From: INOUE, FUMIHIKO; SOUMA, HARUKI; HAYAKAWA, YUKIO
To: SPANSION LLC
Reel/Frame 021587/0286 →
Priority Claims (1)
JP 2007-214097 · Aug 20, 2007 · national
Continuity (1)
Related Publication 20090206388A1 · Aug 20, 2009