Method and structure for forming finFETs with multiple doping regions on a same chip
View Patent ↗A method for fabrication of features for an integrated circuit includes patterning a first semiconductor structure on a surface of a semiconductor device, and epitaxially growing semiconductor material on opposite sides of the first semiconductor structure to form fins. A first angled ion implantation is applied to one side of the first semiconductor structure to dope a respective fin on the one side. The first semiconductor structure is selectively removed to expose the fins. Fin field effect transistors are formed using the fins.
1. A method for fabrication of features for an integrated circuit, comprising:
patterning a first semiconductor structure on a surface of a semiconductor substrate;
epitaxially growing semiconductor material on opposite sides of the first semiconductor structure to form a first fin and a second fin;
applying a first angled ion implantation to one side of the first semiconductor structure to dope the first fin on the one side without doping the second fin;
selectively removing the first semiconductor structure to expose the first fin and the second fin; and
forming fin field effect transistors using the first fin and the second fin.
2. The method as recited in claim 1 , further comprising treating the first structure to permit epitaxial growth on sidewalls of the first structure.
3. The method as recited in claim 1 , further comprising applying a second angled ion implantation to an opposite side of the first semiconductor structure to dope the second without doping the first fin.
4. The method as recited in claim 1 , wherein epitaxially growing semiconductor material includes introducing dopants during epitaxial growth of the semiconductor material.
5. The method as recited in claim 1 , wherein epitaxially growing semiconductor material includes epitaxially growing the semiconductor material such that a width of the semiconductor material includes a size less than a minimum feature size achievable by a lithographic method.
6. The method as recited in claim 1 , wherein the first semiconductor structure includes a material which permits direct epitaxial growth.
7. The method as recited in claim 1 , wherein the first semiconductor structure includes silicon germanium.
8. The method as recited in claim 2 , wherein the first semiconductor structure includes silicon and treating the first semiconductor structure includes forming porous silicon by doping and anodizing.
9. The method as recited in claim 8 , wherein epitaxially growing semiconductor material includes epitaxially growing silicon on the porous silicon of the first semiconductor structure.
10. The method as recited in claim 3 , wherein applying the first angled ion implantation includes doping the one side with a first polarity dopant and applying the second angled ion implantation includes doping the opposite side with a second polarity dopant.
11. The method as recited in claim 3 , wherein applying the first angled ion implantation includes doping the one side with a first dopant density and applying the second angled ion implantation includes doping the opposite side with a second dopant density.
12. A method for fabrication of features for an integrated circuit, comprising:
patterning mandrels on a surface of a semiconductor substrate;
forming spacers about a periphery of the mandrels;
applying a first angled ion implantation to introduce a first doping such that the spacers and mandrels faun a blocking mask to direct the first doping into an underlying semiconductor layer on one side of the blocking mask;
applying a second angled ion implantation in an opposite direction to the first angled ion implantation to introduce a second doping such that the blocking mask directs the second doping into the underlying semiconductor layer on an opposite side of the blocking mask;
selectively removing the mandrels relative to the spacers;
patterning the underlying semiconductor layer using the spacers as an etch mask to form fins with the first doping and fins with second doping;
annealing the fins with the first doping and fins with second doping; and
forming fin field effect transistors using the fins.
13. The method as recited in claim 12 , wherein the first doping includes a first polarity dopant and the second doping includes a second polarity dopant.
14. The method as recited in claim 12 , wherein the first doping includes a first dopant density and the second doping includes a second dopant density.
15. The method as recited in claim 12 , wherein forming spacers includes forming spacers having a feature size less than a minimum feature size achievable by a lithographic method.
16. The method as recited in claim 12 , wherein the fins have a feature size less than a minimum feature size achievable by a lithographic method.