Method for manufacturing SONOS flash memory

1. A method for manufacturing a semiconductor device comprising:

forming a dummy layer on a semiconductor substrate;

forming a groove in the semiconductor substrate while using the dummy layer as a mask;

forming a tunnel insulating film and a trap layer to cover an inner surface of the groove and the dummy layer;

forming a bury layer in the groove and over the trap layer, wherein portions of the trap layer formed over sides of the dummy layer are exposed;

eliminating the trap layer formed above an upper surface of the dummy layer, and at sides of the dummy layer; and

forming a top insulating film to cover a remaining trap layer and an exposed tunnel insulating film.

2. The method according to claim 1 , wherein eliminating the trap layer comprises:

eliminating the trap layer while using the bury layer as a mask.

3. The method according to claim 2 , wherein forming a bury layer comprises:

forming a layer to be formed as the bury layer to fill the groove and to cover the trap layer; and

eliminating the layer to be formed as the bury layer to expose at least the trap layer at the sides of the dummy layer.

4. The method according to claim 1 , further comprising:

eliminating the dummy layer; and

forming a bit line in the semiconductor substrate between the grooves where the dummy layer has been eliminated.

5. The method according to claim 4 , further comprising forming a gate electrode buried in the groove on the top insulating film, wherein forming the bit line comprises performing an ion implantation to the semiconductor substrate while using the gate electrode as a mask.

6. The according to claim 5 , wherein forming the gate electrode comprises:

forming a layer to be formed as a gate electrode to fill the groove and to cover the top insulating film, and

polishing the layer to be formed as the gate electrode to be flush with the dummy layer.

7. The method according to claim 5 , further comprising the steps of:

forming an insulating layer on the bit line to expose an upper surface of the gate electrode; and

forming a word line which is coupled to the gate electrode and intersects with the bit line in a direction of an extension thereof on the insulating layer.

8. The method according to claim 4 , further comprising forming a metal silicide layer on the bit line between the grooves where the dummy layer has been eliminated.

9. The method for according to claim 1 , wherein the dummy layer and the trap layer are formed from a same material.

10. The method according to claim 1 , wherein a silicon nitride is used for forming the dummy layer and the trap layer.