Extremely thin silicon on insulator (ETSOI) complementary metal oxide semiconductor (CMOS) with in-situ doped source and drain regions formed by a single mask

1. A method of fabricating a semiconductor device comprising:

providing a substrate comprising at least a first semiconductor layer overlying a dielectric layer, wherein the first semiconductor layer has a thickness of less than 10 nm; forming a first gate structure directly on a first portion of the first semiconductor layer and a second gate structure directly on a second portion of the first semiconductor layer;

forming a first conductivity in-situ doped first semiconductor material on exposed surfaces of the first portion of the first semiconductor layer adjacent to the first gate structure, and on exposed surfaces of the second portion of the first semiconductor layer adjacent to the second gate structure;

forming a mask atop the second portion of the first semiconductor layer leaving the first conductivity in-situ doped first semiconductor material on the first portion of the first semiconductor layer exposed;

removing the first conductivity in-situ doped first semiconductor material from the first portion of the first semiconductor layer, wherein the first conductivity in-situ doped first semiconductor material remains on the second portion of the first semiconductor layer; forming a second conductivity in-situ doped second semiconductor material on the first portion of the first semiconductor layer, wherein the mask prohibits the second conductivity in-situ doped semiconductor material from being formed atop the second portion of the second semiconductor layer; and

diffusing dopant from the second conductivity in-situ doped second semiconductor material and the first conductivity in-situ doped first semiconductor material into the first semiconductor layer to form extension regions.

2. The method of claim 1 , wherein the first portion of the first semiconductor layer is electrically isolated from the second portion of the first semiconductor layer.

3. The method of claim 1 , wherein the substrate further comprising a second semiconductor layer separated from the overlying first semiconductor layer by the dielectric layer.

4. The method of claim 1 , wherein the forming of the first conductivity in-situ doped first semiconductor material comprises epitaxial growth of p-type doped SiGe.

5. The method of claim 4 , wherein the p-type doped SiGe comprise a dopant concentration ranging from 1×10 19 atoms/cm 3 to 5×10 20 atoms/cm 3 .

6. The method of claim 5 , wherein a p-type dopant of the p-type doped SiGe comprises boron, aluminum, gallium or indium.

7. The method of claim 1 , wherein the forming of the mask comprises forming a dielectric stack over the first conductivity in-situ doped first semiconductor material that is present on the first portion of the first semiconductor layer and on the second portion of the first semiconductor layer; forming a second dielectric layer over the first dielectric layer, forming a photoresist mask on the dielectric stack atop the second portion of the first semiconductor layer; and etching the dielectric stack selective to the photoresist mask and the first conductivity in-situ doped first semiconductor material.

8. The method of claim 7 , wherein the dielectric stack comprises an oxide present on the first portion of the first semiconductor layer and on the second portion of the first semiconductor layer, and a nitride that is present on the oxide.

9. The method of claim 1 , wherein the forming of the second conductivity in-situ doped second semiconductor material on the first portion of the first semiconductor layer comprises epitaxial growth of n-type doped Si:C.

10. The method of claim 9 , wherein the n-type doped Si:C comprises a dopant concentration ranging from 1×10 18 atoms/cm 3 to 2×10 21 atoms/cm 3 .

11. The method of claim 5 , wherein a n-type dopant of the n-type doped Si:C comprises antimony, arsenic or phosphorous.

12. The method of claim 1 , wherein following forming the second conductivity in-situ doped second semiconductor material, the mask is removed by etching.

13. The method of claim 1 , wherein the diffusing dopant from the second conductivity in-situ doped second semiconductor material and the first conductivity in-situ doped first semiconductor material into the first semiconductor layer comprises annealing.

14. The method of claim 13 , wherein the annealing comprises rapid thermal annealing, furnace annealing, flash lamp annealing or laser annealing.

15. The method of claim 1 , wherein the second conductivity in-situ doped second semiconductor material and the first conductivity in-situ doped first semiconductor material provides raised source and drain regions.

16. A method of fabricating an electronic structure comprising:

providing a semiconductor on insulator (SOI) substrate comprising an SOI semiconductor layer having a thickness of less than 5 nm;

forming an first conductivity doped first semiconductor material on exposed surfaces of the first portion of the SOI semiconductor layer, and on exposed surfaces of the second portion of the SOI semiconductor layer;

forming a mask overlying the second portion of the SOI semiconductor layer; removing the first conductivity in-situ doped first semiconductor material from the first portion of the SOI semiconductor layer, wherein the first conductivity in-situ doped first semiconductor material remains on the second portion of SOI semiconductor layer;

forming a second conductivity in-situ doped second semiconductor material on the first portion of the SOI semiconductor layer, wherein a mask prohibits the second conductivity in-situ doped second semiconductor material from being formed atop the second portion of the SOI semiconductor layer; and

diffusing dopant from the second conductivity in-situ doped second semiconductor material and the first conductivity in-situ doped first semiconductor material into the first semiconductor layer to form dopant regions.

17. The electric structure of claim 16 , wherein the electric structure is a MOSFET, FinFET, multiple gate MOSFET, or nanowire.