Structure for implementing memory array device with built in computation capability
View Patent ↗A design structure embodied in a machine readable medium used in a design process includes computational memory device having an array of memory cells arranged in rows and columns, and a pair of read word lines associated with each row of the array. The array is configured to implement, for a given cycle, either a read operation of data contained in a single selected row, or one of a plurality of different bit wise logical operations on data contained in multiple selected rows.
1. A design structure embodied in a non-transitory, machine readable medium used in a design process, the design structure comprising:
a computational memory device including an array of memory cells arranged in rows and columns; and
a pair of read word lines associated with each row of the array;
wherein the array is configured to implement, for a first cycle, a read operation of data contained in a single selected row, and, for a second cycle, one of a plurality of different bit wise logical operations on data contained in multiple selected rows;
wherein the design structure comprises a netlist describing the computational memory device.
2. The design structure of claim 1 , wherein the plurality of different bit wise logical operations implementable by the array include OR operations, NAND operations, and combinations thereof.
3. The design structure of claim 2 , wherein each of the memory cells further comprise:
an SRAM storage device configured to store a data bit therein;
a first NFET stack associated with a true data node of the SRAM storage device and a first of the pair of read word lines of the corresponding row of the cell; and
a second NFET stack associated with a complementary data node of the SRAM storage device and a second of the pair of read word lines of the corresponding row of the cell;
wherein both the first and second NFET stacks are configured to discharge a precharged read bit line associated with the corresponding column of the array, depending upon the state of the associated read word line and the associated data node of the SRAM storage device.
4. The design structure of claim 3 , wherein output bits of the memory array comprise inverted values of the voltages of the read bit lines.
5. The design structure of claim 4 , wherein for the read operation of data contained in a single selected row, the first read word line of the selected row is activated, the second read word line of the selected row is deactivated, and the first and second read word lines of all other non-selected rows are deactivated.
6. The design structure of claim 4 , wherein for the OR operation of data contained in multiple selected rows, the first read word line of each of the multiple selected rows is activated, the second read word line of each of the multiple selected rows is deactivated, and the first and second read word lines of all other non-selected rows are deactivated.
7. The design structure of claim 4 , wherein for the NAND operation of data contained in multiple selected rows, the second read word line of each of the multiple selected rows is activated, the first read word line of each of the multiple selected rows is deactivated, and the first and second read word lines of all other non-selected rows are deactivated.
8. The design structure of claim 4 , wherein for a combination of OR and NAND operations of data contained in multiple selected rows, either the first read word line or the second read word line of each of the multiple selected rows is activated, and the first and second read word lines of all other non-selected rows are deactivated.
9. The design structure of claim 2 , wherein each of the memory cells further comprise:
a first SRAM storage device configured to store a first data bit therein;
a second SRAM storage device configured to store a second data bit therein, the first and second SRAM storage device thereby forming a ternary cell;
a first NFET stack associated with a true data node of the first SRAM storage device and a first of the pair of read word lines of the corresponding row of the cell; and
a second NFET stack associated with a true data node of the second SRAM storage device and a second of the pair of read word lines of the corresponding row of the cell;
wherein both the first and second NFET stacks are configured to discharge a precharged read bit line associated with the corresponding column of the array, depending upon the state of the associated read word line and the true data node of the associated SRAM storage device.
10. The design structure of claim 9 , wherein output bits of the memory array comprise inverted values of the voltages of the read bit lines.
11. The design structure of claim 10 , wherein for the read operation of data contained in a single selected row, the first read word line of the selected row is activated, the second read word line of the selected row is deactivated, and the first and second read word lines of all other non-selected rows are deactivated.
12. The design structure of claim 10 , wherein for the OR operation of data contained in multiple selected rows, the first read word line of each of the multiple selected rows is activated, the second read word line of each of the multiple selected rows is deactivated, and the first and second read word lines of all other non-selected rows are deactivated.
13. The design structure of claim 10 , wherein for the NAND operation of data contained in multiple selected rows, the second read word line of each of the multiple selected rows is activated, the first read word line of each of the multiple selected rows is deactivated, and the first and second read word lines of all other non-selected rows are deactivated.
14. The design structure of claim 10 , wherein for a combination of OR and NAND operations of data contained in multiple selected rows, either the first read word line or the second read word line of each of the multiple selected rows is activated, and the first and second read word lines of all other non-selected rows are deactivated.
15. The design structure of claim 2 , wherein each of the memory cells further comprise:
an SRAM storage device configured to store a data bit therein;
a first NFET stack associated with a true data node of the SRAM storage device and a first of the pair of read word lines of the corresponding row of the cell; and
a second NFET stack associated with a complementary data node of the SRAM storage device and a second of the pair of read word lines of the corresponding row of the cell;
the first NFET stack configured to discharge a first precharged read bit line associated with the corresponding column of the array, and the second NFET stack configured to discharge a second precharged read bit line associated with the corresponding column of the array so as to define a 2-port read device; and
circuitry configured to tie the first and second read bit lines together during the implementation of the bit wise logical operations on data contained in multiple selected rows.
16. The design structure of claim 1 , wherein the design structure resides on storage medium as a data format used for the exchange of layout data of integrated circuits.
17. The design structure of claim 1 , wherein the design structure includes at least one of test data files, characterization data, verification data, programming data, or design specifications.