Method, structure, and design structure for an impedance-optimized microstrip transmission line for multi-band and ultra-wide band applications
View Patent ↗A method, structure, and design structure for an impedance-optimized microstrip transmission line for multi-band and ultra-wide band applications. A method includes: forming a plurality of openings in a ground plane associated with a signal line; forming a plurality of capacitance plates in the plurality of openings; and connecting the plurality of capacitance plates to the signal line with a plurality of posts extending between the signal line and the plurality of capacitance plates.
1. A semiconductor transmission line, comprising:
a signal line formed over a substrate;
a plurality of posts extending from the signal line;
a plurality of plates corresponding to the plurality of posts; and
a ground return line,
wherein each one of the plurality of posts has a first end contacting the signal line and a second end contacting a respective one of the plurality of plates.
2. The semiconductor transmission line of claim 1 , wherein:
the ground return line and the plurality of plates are formed in a lowermost wiring level, and
the signal line is formed in an uppermost wiring level.
3. The semiconductor transmission line of claim 1 , further comprising an insulator between a bottom of the plurality of plates and a top of the substrate.
4. The semiconductor transmission line of claim 1 , wherein each one of the plurality of posts spans plural levels between the signal line and a layer containing the plurality of plates.
5. The semiconductor transmission line of claim 1 , further comprising two coplanar waveguide side-shields formed in a same level as the signal line, wherein the coplanar waveguide side-shields are tied to the ground return line.
6. The semiconductor transmission line of claim 1 , wherein:
the ground return line comprises two coplanar waveguide side-shields that are formed in a same level as the signal line, and
the transmission line is devoid of a ground plane beneath the signal line.
7. The semiconductor transmission line of claim 1 , wherein the ground return line is formed in a same plane as the plurality of plates.
8. The semiconductor transmission line of claim 7 , wherein:
the ground return line comprises a plurality of openings, and
each one of the plurality of plates is arranged in a respective one of the plurality of openings.
9. The semiconductor transmission line of claim 8 , wherein the plurality of openings and the plurality of plates are sized to add an amount of capacitance corresponding to a predetermined amount of decrease of an inductance.
10. The semiconductor transmission line of claim 8 , wherein the plurality of plates are structured and arranged to interact with the substrate to add capacitance to the signal line at frequencies less than a threshold frequency.
11. The semiconductor transmission line of claim 10 , wherein
the substrate comprises silicon, and
the threshold frequency is a relaxation frequency of the substrate.
12. A design structure tangibly embodied in a non-transitory machine readable medium for designing, manufacturing, or testing an integrated circuit, the design structure comprising:
a signal line formed over a substrate;
a plurality of posts extending from the signal line;
a plurality of plates corresponding to the plurality of posts; and
a ground return line,
wherein each one of the plurality of posts has a first end contacting the signal line and a second end contacting a respective one of the plurality of plates.
13. The design structure of claim 12 , wherein the design structure comprises a netlist.
14. The design structure of claim 12 , wherein the design structure resides on storage medium as a data format used for the exchange of layout data of integrated circuits.
15. The design structure of claim 12 , wherein the design structure resides in a programmable gate array.
16. A method for controlling characteristic impedance in a transmission line, comprising:
forming a plurality of openings in a ground plane associated with a signal line;
forming a plurality of capacitance plates in the plurality of openings; and
connecting the plurality of capacitance plates to the signal line with a plurality of posts extending between the signal line and the plurality of capacitance plates.
17. The method of claim 16 , further comprising sizing the capacitance plates to provide additional capacitance to the signal line at frequencies below a relaxation frequency of a substrate on which the transmission line is formed, wherein the additional capacitance corresponds to a determined loss of induction based on frequency.
18. The method of claim 16 , further comprising forming coplanar waveguide side-shields in a same plane as the signal line, wherein the coplanar waveguide side-shields are tied to ground.
19. The method of claim 16 , wherein the forming the plurality of capacitance plates comprises forming the plurality of capacitance plates in a same layer as the ground plane.
20. The method of claim 19 , further comprising forming the signal line in a layer above the ground plane.