Ultrathin spacer formation for carbon-based FET

1. A method for formation of a carbon-based field effect transistor (FET), the method comprising:

depositing a first dielectric layer on a carbon layer located on a substrate;

forming a gate electrode on the first dielectric layer;

etching an exposed portion of the first dielectric layer to expose a portion of the carbon layer;

depositing a second dielectric layer over the gate electrode to form a spacer, wherein the second dielectric layer is deposited by atomic layer deposition (ALD), and wherein the second dielectric layer does not form on the exposed portion of the carbon layer; and

forming source and drain contacts on the carbon layer and forming a gate contact on the gate electrode to form the carbon-based FET.

2. The method of claim 1 , wherein the first dielectric layer comprises a high k material.

3. The method of claim 2 , wherein depositing the first dielectric layer comprises depositing a seed layer on the carbon layer, and then depositing the high k material by ALD on the seed layer.

4. The method of claim 2 , wherein depositing the first dielectric layer comprises treating the carbon layer with ozone, and then depositing the high k material by ALD on the carbon layer.

5. The method of claim 1 , wherein the gate electrode comprises a gate metal layer located on the first dielectric layer, and a nitride layer located over the gate metal layer.

6. The method of claim 5 , wherein the gate metal layer comprises palladium, and the carbon-based FET comprises a p-type FET.

7. The method of claim 5 , wherein the gate metal layer comprises aluminum, and the carbon-based FET comprises an n-type FET.

8. The method of claim 5 , wherein the nitride layer acts as a hard mask during the etching of an exposed portion of the first dielectric layer.

9. The method of claim 1 , wherein the etching of an exposed portion of the first dielectric layer comprises a high k wet etch.

10. The method of claim 1 , wherein forming source and drain metal contacts on the carbon layer comprises:

depositing a metal layer over the exposed portion of the carbon layer and the second dielectric layer;

performing chemical mechanical polishing (CMP) to expose a portion of the second dielectric layer that is located on top of the gate electrode;

patterning the metal layer to remove a portion of the metal layer that is not located on the carbon layer; and

forming the source and drain metal contacts on the portion of the metal layer that is located on the carbon layer.

11. The method of claim 1 , further comprising forming a passivation layer comprising one of oxide and nitride over the carbon-based FET.

12. The method of claim 1 , wherein the carbon layer comprises one of a carbon nanotube and one or more sheets of graphene.

13. The method of claim 1 , wherein the spacer comprises a low k material.