Manufacturing stacked semiconductor device
A method in accordance with an embodiment of the invention can include forming fan-out wirings on an insulating layer formed on a wafer. Additionally, electrodes of a plurality of semiconductor chips stacked on the fan-out wirings can be electrically coupled with the fan-out wirings. The wafer can be removed.
1. A method comprising:
forming an insulating layer on and in contact with a wafer;
after the forming of the insulating layer, forming fan-out wirings on the insulating layer;
after the forming of the fan-out wirings, stacking a plurality of semiconductor chips on the fan-out wirings using adhesive between each of the plurality of semiconductor chips and the insulating layer;
after the stacking of the plurality of semiconductor chips, electrically connecting electrodes of the plurality of semiconductor chips to the fan-out wirings;
after the electrically connecting of the electrodes, the insulating layer comprising the formed on fan-out wirings is free of an electrical conductor in the insulating layer; and
after the electrically connecting of the electrodes, removing the wafer.
2. The method of claim 1 , further comprising:
resin-sealing the semiconductor chips stacked on the fan-out wirings.
3. The method of claim 2 , wherein said electrically connecting comprises:
forming a seed metal layer over the plurality of semiconductor chips stacked on the fan-out wirings;
forming a photoresist layer over the seed metal layer and the plurality of semiconductor chips stacked on the fan-out wirings;
forming an opening portion within the photoresist layer that extends beyond the electrodes of the plurality of semiconductor chips;
forming metal wiring inside the opening portion; and
removing the first photoresist layer.
4. The method of claim 2 , wherein:
the electrodes serve as side-wall electrodes and have side surfaces that are coplanar with side surfaces of the semiconductor chips.
5. The method of claim 2 , wherein the forming the fan-out wirings comprises:
forming a seed metal layer on a surface of the insulating layer;
after the forming of the seed metal layer, forming a photoresist layer on the surface of the insulating layer; and
removing the photoresist layer at regions.
6. The method of claim 1 , further comprising:
forming a lead-out wiring above the plurality of semiconductor chips.
7. The method of claim 6 , wherein the forming the lead-out wiring comprises:
forming a seed metal layer over the plurality of semiconductor chips stacked on the fan-out wirings;
forming a photoresist layer over the seed metal layer and the plurality of semiconductor chips stacked on the fan-out wirings;
forming an opening portion within the photoresist layer that extend from an upper surface of said photoresist layer to an upper surface of the seed metal layer; and
forming the lead-out wiring inside the opening portion.
8. The method of claim 7 , further comprising:
forming a resin layer over the lead-out wiring and the plurality of semiconductor chips stacked on the fan-out wirings; and
thinning the resin layer until the uppermost surface of the lead-out wiring is exposed.
9. The method of claim 1 , wherein said electrically connecting comprises:
forming a seed metal layer over the semiconductor chips stacked on the fan-out wirings;
forming a photoresist layer over the seed metal layer and the plurality of semiconductor chips stacked on the fan-out wirings;
forming an opening portion within the photoresist layer that extends beyond the electrodes of the plurality of semiconductor chips;
forming metal wiring inside the opening portion; and
removing the first photoresist layer.
10. The method of claim 1 , wherein:
the electrodes serve as side-wall electrodes and have side surfaces that are coplanar with side surfaces of the semiconductor chips.
11. The method of claim 1 , wherein:
the electrodes serve as side-wall electrodes and have side surfaces that are coplanar with side surfaces of the semiconductor chips; and
the forming the side-wall electrodes comprises:
forming a first protective film at portions on an upper surface of the semiconductor chips other than portions where pads are formed;
forming a seed metal layer on an upper surface of the semiconductor chips;
forming a second photoresist layer on the upper surface of the semiconductor chips;
removing from the second photoresist layer regions in which one surface is coplanar with a side surface of the semiconductor chips and in which the pads exist downward in a stacking direction;
forming the side-wall electrodes in said regions;
removing the second photoresist layer; and
removing portions of the seed metal layer.
12. The method of claim 1 , wherein the forming the fan-out wirings comprises:
forming a seed metal layer on a surface of the insulating layer;
after the forming of the seed metal layer, forming a photoresist layer on the insulating layer; and
removing the photoresist layer at regions.
13. A method comprising:
forming an insulating layer on and in contact with a wafer;
after the forming of the insulating layer, forming fan-out wirings on the insulating layer;
after the forming of the fan-out wirings, stacking a plurality of semiconductor chips on the fan-out wirings using adhesive between each of the plurality of semiconductor chips and the insulating layer;
after the stacking of the plurality of semiconductor chips, electrically connecting electrodes of the plurality of semiconductor chips to the fan-out wirings;
after the electrically connecting of the electrodes, the insulating layer comprising the formed on fan-out wirings is free of a through hole and an electrical conductor in the insulating layer;
after the electrically connecting of the electrodes, forming lead-out wirings above the plurality of semiconductor chips; and
removing the wafer.
14. The method of claim 13 , wherein the forming the lead-out wirings comprises:
forming a seed metal layer over the plurality of semiconductor chips stacked on the fan-out wirings;
forming a photoresist layer over the seed metal layer and the plurality of semiconductor chips stacked on the fan-out wirings;
forming opening portions within the photoresist layer that extend from an upper surface of said photoresist layer to an upper surface of the seed metal layer;
forming the lead-out wirings inside the opening portions;
removing the photoresist layer; and
removing portions of the seed metal layer.
15. The method of claim 14 , further comprising:
forming a resin layer over the lead-out wirings and the plurality of semiconductor chips stacked on the fan-out wirings; and
thinning the resin layer until the uppermost surfaces of the lead-out wirings are exposed.
16. The method of claim 13 , further comprising:
resin-sealing the semiconductor chips stacked on the fan-out wirings.
17. The method of claim 16 , wherein:
the electrodes serve as side-wall electrodes and have side surfaces that are coplanar with side surfaces of the semiconductor chips.
18. The method of claim 13 , further comprising:
forming a lead-out wiring above the plurality of semiconductor chips.
19. The method of claim 13 , wherein:
the electrodes serve as side-wall electrodes and have side surfaces that are coplanar with side surfaces of the semiconductor chips.
20. The method of claim 13 , wherein the forming the fan-out wirings comprises:
forming a seed metal layer on a surface of the insulating layer;
after the forming of the seed metal layer, forming a photoresist layer on the insulating layer; and
removing the photoresist layer at regions.