Sealed air gap for semiconductor chip

1. A semiconductor chip, comprising:

a substrate;

a dielectric layer over the substrate;

a gate within the dielectric layer, the gate including a sidewall;

a contact contacting a portion of the gate and a portion of the sidewall;

a sealed air gap between the sidewall, the dielectric layer and the contact; and

a dielectric oxygen diffusion barrier within the sealed air gap and substantially over the gate and a source and a drain in the substrate adjacent to the gate.

2. The chip of claim 1 , further comprising a protective spacer over a gate dielectric of the gate.

3. The chip of claim 1 , wherein the contact comprises at least one of copper and tungsten.

4. The chip of claim 1 , further comprising a shallow trench isolation adjacent to the gate in the substrate.