Silicon based microchannel cooling and electrical package
View Patent ↗A chip package includes: a substrate; a plurality of conductive connections in contact with the silicon carrier; a silicon carrier in a prefabricated shape disposed above the substrate, the silicon carrier including: a plurality of through silicon vias for providing interconnections through the silicon carrier to the chip; liquid microchannels for cooling; a liquid coolant flowing through the microchannels; and an interconnect to one or more chips or chip stacks.
1. A chip package comprising:
a substrate;
a first array of small, highly thermally conductive metallic balls from 2.0 to 20 microns in diameter between a silicon carrier and the substrate;
the silicon carrier for a chip in a prefabricated shape disposed above the substrate, the silicon carrier comprising:
a plurality of through silicon vias providing electrical interconnections through the silicon carrier to the chip;
a dielectric layer disposed between the silicon carrier and the plurality of through silicon vias;
liquid microchannels cooling the chip;
a liquid coolant flowing through the liquid microchannels; and
a second array of small, highly thermally conductive metallic connections attaching one or more chips or chip stacks to the silicon carrier; and
a cooling cap disposed over the chip, said cooling cap comprising fluid microchannels further cooling the chip.
2. The chip package of claim 1 wherein the interconnection to the chip provides both electrical and thermal transport and comprises metallic conductors.
3. The chip package of claim 1 wherein the plurality of through silicon vias are formed by etching into the silicon carrier.
4. The chip package of claim 1 wherein the liquid microchannels are formed by etching into the silicon carrier.
5. The chip package of claim 1 wherein the first array comprises an array selected from a group consisting of:
copper to copper interconnections;
metallic interconnections;
solder micro-joints;
controlled collapse chip connections;
thin height, large area connections;
an array of connections of equal size; and
a combination of smaller thin connections and large area thin interconnections.
6. The chip package of claim 1 wherein the substrate is attached to a card, board, or other surface with an area array selected from a group consisting of:
a ball grid array;
a column grid array;
a pin grid array;
a land grid array; and
a high density connector.
7. The chip package of claim 1 wherein the cooling cap adheres to the chip with an adhesive.
8. The chip package of claim 1 further comprising a thermal interface material disposed between the cooling cap and the chip to transfer heat from the chip.
9. The chip package of claim 8 wherein the thermal interface material is further disposed between the chip and the silicon carrier.
10. The chip package of claim 1 wherein the plurality of through silicon vias provide electrical interconnections.
11. The chip package of claim 10 wherein the electrical interconnections are vertical.
12. The chip package of claim 1 wherein the cooling cap may also provide electrical interconnection to the chip or chip stack for power delivery and signal interconnection.
13. The chip package of claim 1 wherein the plurality of through silicon vias further comprise optical interconnections.
14. The chip package of claim 1 further comprising a second silicon carrier disposed above the chip cooling the top and bottom of the chip, the second silicon carrier comprising pre-formed through silicon vias for interconnections and liquid microchannels for cooling.