Microcontroller with integrated graphical processing unit
A microcontroller with an integrated special instruction processing unit and a programmable cycle state machine. The special instruction processing unit allows offloading of intensive processing of output data and the programmable cycle state machine minimizes the amount of customized, off chip circuitry necessary to connect the microcontroller to an external display.
1. A microcontroller integrated circuit comprising:
a first central processing unit (CPU);
a memory;
a programmable cycle state machine;
a special instruction processing unit (SIPU) comprising an opcode interface, wherein the SIPU is operable to read and write data to said memory and to receives instructions directly from the CPU through said opcode interface and comprises an arithmetic logic unit (ALU) and a register bank coupled with the ALU;
a connection to an output device;
wherein the SIPU manipulates multiple values in the memory responsive to a command from the CPU by means of said ALU and register bank;
wherein the programmable cycle state machine continuously transfers data from the memory to the output device; and
wherein the programmable cycle state machine periodically transmits a control signal to the output device to coordinate the data transfers with the input timing requirements of the output device.
2. The microcontroller according to claim 1 ,
wherein the output device is a liquid crystal display (LCD),
wherein bit-depth of the LCD is between 1 bit and 16 bits,
wherein each pixel is represented by one value or three values, and
wherein the geometry of the LCD is between 64 by 64 pixels and 854 by 480 pixels.
3. The microcontroller according to claim 1 , wherein the CPU has a data path no wider than 16-bits and performs fewer than 60 million instructions per second.
4. The microcontroller according to claim 1 , wherein the programmable cycle state machine supports the control signal timing required by at least four different graphics display technologies from a set consisting of:
monochrome liquid crystal display (LCD),
color super twisted nematic (STN) liquid crystal display,
double-layer super twisted nematic (DSTN) liquid crystal display,
color thin-film transistor (TFT) liquid crystal display,
zero-power bistable display,
plasma display,
liquid crystal on silicon device,
digital micromirror device,
light-emitting diode panel,
organic light-emitting diode (OLED) display.
5. The microcontroller according to claim 1 , further comprising a direct memory access (DMA) controller with one high priority port and at least three low priority ports,
wherein the high priority port of the DMA controller is connected to the programmable cycle state machine;
wherein a first low priority port of the DMA controller is connected to the memory and a second and third low priority port of the DMA controller is connected to the SIPU.
6. The microcontroller according to claim 1 , wherein the SIPU is operable to perform block transfer operations by means of a block transfer instruction.
7. The microcontroller according to claim 6 , wherein the SIPU can perform the logical operations of XOR, OR, and AND.
8. The microcontroller according to claim 6 , wherein a SIPU instruction set includes a background fill operation, a pixel set operation, and a line draw operation.
9. The microcontroller according to claim 8 , wherein the SIPU instruction set includes a picture-in-picture operation.
10. The microcontroller according to claim 5 , further comprising a color lookup table (CLT) between the DMA controller and the programmable cycle state machine.
11. A microcontroller integrated circuit comprising:
a central processing unit (CPU),
memory,
a special instruction processing unit (SIPU) comprising an opcode interface, wherein the SIPU receives instructions directly from the CPU through said opcode interface and comprises an arithmetic logic unit (ALU) and a register bank coupled with the ALU,
a programmable cycle state machine, and
a direct memory access (DMA) controller comprising four ports coupled to said CPU, memory, SIPU, and programmable cycle state machine, respectively;
wherein processing of output data stored in said memory is performed by the SIPU by means of said ALU and register bank and said programmable cycle state machine outputs said output data stored in said memory to an external device, freeing CPU cycles for other tasks.
12. The microcontroller according to claim 11 , wherein a SIPU instruction set includes the logical operations of XOR, OR and AND.
13. The microcontroller according to claim 11 , wherein a SIPU instruction set includes a background fill operation, a pixel set operation, and a line draw operation.
14. The microcontroller according to claim 11 , further comprising a color lookup table.
15. The microcontroller according to claim 11 , wherein the SIPU interfaces with at least two ports on the DMA controller.
16. A microcontroller integrated circuit comprising:
a 16-bit central processing unit (CPU),
memory,
a special instruction processing unit (SIPU) comprising an opcode interface, wherein the SIPU receives instructions directly from the CPU through said opcode interface and comprises an arithmetic logic unit (ALU) and a register bank coupled with the ALU,
a programmable cycle state machine, and
a direct memory access (DMA) controller comprising first and second, third and fourth ports coupled with the CPU, SIPU, said memory, and said programmable cycle state machine, respectively;
wherein the memory stores display data and the microcontroller can display graphical information on a variety of sizes, color depths, and technologies of liquid crystal displays (LCD) using said CPU, memory, SIPU and said programmable cycle state machine, wherein the programmable cycle state machine provides the display data to said LCD, such that said CPU still has sufficient CPU bandwidth to respond in real-time to external interrupts.
17. The microcontroller according to claim 16 ,
wherein the output device is a liquid crystal display (LCD),
wherein bit-depth of the LCD is between 1 bit and 16 bits,
wherein each pixel is represented by one value or three values, and
wherein the geometry of the LCD is between 64 by 64 pixels and 854 by 480 pixels.
18. The microcontroller according to claim 17 , wherein the CPU has a data path no wider than 16-bits and performs fewer than 60 million instructions per second.
19. The microcontroller according to claim 16 , wherein the SIPU has read access to two ports on the DMA controller.
20. The microcontroller according to claim 19 , wherein the SIPU has write access to a third port on the DMA controller.