Strained fully depleted silicon on insulator semiconductor device
A semiconductor substrate is provided having an insulator thereon with a semiconductor layer on the insulator. A deep trench isolation is formed, introducing strain to the semiconductor layer. A gate dielectric and a gate are formed on the semiconductor layer. A spacer is formed around the gate, and the semiconductor layer and the insulator are removed outside the spacer. Recessed source/drain are formed outside the spacer.
1. A semiconductor device comprising:
a silicon substrate having a buried oxide layer insulator thereon and a silicon layer on the buried oxide layer insulator;
a gate dielectric and a gate on the silicon layer;
a liner around the gate and on the silicon layer;
a spacer on the liner around the gate;
recessed source/drain formed through selective epitaxial growth outside the spacer; and
a deep trench isolation spaced apart from the spacer;
wherein a selected portion-of the buried oxide layer insulator disposed between the gate and the deep trench isolation is removed to result in exposed silicon substrate portions, such that said buried oxide layer is immediately adjacent said recessed source/drain, and said recessed source/drain is uniformly grown on said exposed silicon substrate portions.
2. The semiconductor device of claim 1 wherein the recessed source/drain formed through selective epitaxial growth outside the spacer further comprises recessed carbon doped silicon source/drain formed through selective epitaxial growth outside the spacer, introducing strain to the silicon layer.
3. The semiconductor device of claim 1 wherein the recessed source/drain formed through selective epitaxial growth outside the spacer further comprises recessed silicon germanium source/drain formed through selective epitaxial growth outside the spacer, introducing strain to the silicon layer.
4. The semiconductor device of claim 1 , wherein the liner further lines at least a top of the deep trench isolation.
5. The semiconductor device of claim 1 , wherein the spacer is further disposed within the deep trench isolation.
6. The semiconductor device of claim 1 , further comprising a silicide layer on the gate and the recessed source/drain.
7. The semiconductor device of claim 1 , wherein the silicon layer is less than 100 Å thick.
8. The semiconductor device of claim 1 , wherein the deep trench isolation is formed before the recessed source/drain are formed and the recessed source/drain comprise a primary strain control for the silicon layer.
9. The semiconductor device of claim 1 , wherein the deep trench isolation is formed after the recessed source/drain are formed and the recessed source/drain and deep trench isolation comprise adjunct strain controls for the silicon layer.
10. A semiconductor device comprising:
a semiconductor substrate having a buried oxide layer insulator thereon and a channel layer on the buried oxide layer insulator;
a gate dielectric and a gate on the channel layer;
a liner around the gate and on the channel layer;
a spacer on the liner around the gate;
recessed source/drain formed through selective epitaxial growth outside the spacer and through the channel layer;
wherein selected portions of the buried oxide layer insulator not disposed under the gate are removed to result in exposed semiconductor substrate portions, such that said buried oxide layer is immediately adjacent said recessed source/drain, and said recessed source/drain is uniformly grown on said exposed semiconductor substrate portions.
11. The semiconductor device of claim 7 , wherein the recessed source/drain further comprise recessed carbon doped silicon source/drain formed through selective epitaxial growth outside the spacer, introducing strain to the channel layer.
12. The semiconductor device of claim 7 , wherein the recessed source/drain further comprise recessed silicon germanium source/drain formed through selective epitaxial growth outside the spacer, introducing strain to the channel layer.
13. The semiconductor device of claim 7 , wherein the channel layer is less than 100 Å thick.
14. The semiconductor device of claim 7 , further comprising a deep trench isolation spaced apart from the spacer.
15. The semiconductor device of claim 14 , wherein the liner further lines at least a top of the deep trench isolation.
16. The semiconductor device of claim 14 , wherein the spacer further disposed within the deep trench isolation.
17. The semiconductor device of claim 14 , wherein the deep trench isolation is formed before the recessed source/drain are formed and the recessed source/drain comprise a primary strain control for the channel layer.
18. The semiconductor device of claim 14 , wherein the deep trench isolation is formed after the recessed source/drain are formed and the recessed source/drain and deep trench isolation comprise adjunct strain controls for the channel layer.