Nitride gate dielectric for graphene MOSFET

1. A method of forming a semiconductor structure comprising:

providing a substrate;

forming a graphene layer on the substrate;

depositing a nitride layer on the graphene layer;

forming a source electrode and a drain electrode on the graphene layer, the source electrode and drain electrode being spaced apart by a predetermined dimension, the nitride layer extending the entire predetermined dimension between the source electrode and drain electrode; and

forming a gate electrode on the nitride layer, wherein the nitride layer is a gate dielectric for the gate electrode.

2. The method of claim 1 further comprising forming a spacer adjacent the gate electrode and on the nitride layer.

3. The method of claim 1 wherein forming a source electrode and a drain electrode occurs prior to depositing a nitride layer and wherein depositing a nitride layer includes depositing the nitride layer on a sidewall of the source electrode and a sidewall of the drain electrode.

4. The method of claim 1 wherein the nitride layer is selected from the group consisting of aluminum nitride, silicon nitride, hafnium nitride and zirconium nitride.

5. The method of claim 1 wherein the wherein the step of forming is carried out using a pre-formed graphene.

6. The method of claim 1 wherein the graphene layer is in direct contact with the substrate and the nitride layer is in direct contact with the graphene layer.

7. A method of forming a semiconductor structure comprising:

providing a substrate;

forming a graphene layer on the substrate;

depositing a nitride layer on the graphene layer;

forming a source electrode and a drain electrode on the graphene layer, the source electrode and drain electrode being spaced apart by a predetermined dimension, the nitride layer extending at least part of the predetermined dimension between the source electrode and drain electrode; and

forming a gate electrode on the nitride layer, wherein the nitride layer is a gate dielectric for the gate electrode and further comprising patterning the nitride layer so as to remove the nitride layer from portions of the graphene layer.

8. The method of claim 7 wherein the graphene layer is in direct contact with the substrate and the nitride layer is in direct contact with the graphene layer.

9. The method of claim 7 wherein the nitride layer is selected from the group consisting of aluminum nitride, silicon nitride, hafnium nitride and zirconium nitride.

10. The method of claim 7 wherein the wherein the step of forming is carried out using a pre-formed graphene.

11. The method of claim 7 wherein patterning comprises removing the nitride layer not covered by the gate electrode.

12. The method of claim 11 further comprising forming a spacer adjacent the gate electrode and on the graphene layer.

13. A semiconductor structure comprising:

a substrate;

a graphene layer on the substrate;

a source electrode and a drain electrode on the graphene layer, the source electrode and drain electrode being spaced apart by a predetermined dimension;

a nitride layer on the graphene layer between the source electrode and drain electrode; and

a gate electrode on the nitride layer, wherein the nitride layer is a gate dielectric for the gate electrode wherein the nitride layer extends only under the gate electrode.

14. The semiconductor structure of claim 13 further comprising a spacer adjacent the gate electrode and on the graphene layer.

15. The semiconductor structure of claim 13 wherein the graphene layer is in direct contact with the substrate and the nitride layer is in direct contact with the graphene layer.

16. The semiconductor structure of claim 13 wherein the nitride layer can be aluminum nitride, silicon nitride, hafnium nitride or zirconium nitride.

17. A semiconductor structure comprising:

a substrate;

a graphene layer on the substrate;

a source electrode and a drain electrode on the graphene layer, the source electrode and drain electrode being spaced apart by a predetermined dimension;

a nitride layer on the graphene layer between the source electrode and drain electrode, wherein the nitride layer extends the entire predetermined dimension between the source electrode and the drain electrode; and

a gate electrode on the nitride layer, wherein the nitride layer is a gate dielectric for the gate electrode.

18. The semiconductor structure of claim 17 further comprising a spacer adjacent the gate electrode and on the nitride layer.

19. The semiconductor structure of claim 17 wherein the nitride layer extends the entire predetermined dimension between the source electrode and the drain electrode and continues up a sidewall of the source electrode and a sidewall of the drain electrode.

20. The semiconductor structure of claim 17 wherein the nitride layer can be aluminum nitride, silicon nitride, hafnium nitride or zirconium nitride.

21. The semiconductor structure of claim 17 wherein the graphene layer is in direct contact with the substrate and the nitride layer is in direct contact with the graphene layer.

22. The semiconductor structure of claim 17 wherein the substrate is selected from the group consisting of a semiconductor substrate, an insulator substrate, a polymer substrate, a layered substrate and combinations of any of the foregoing substrates.

23. The semiconductor structure of claim 22 wherein the semiconductor substrate is silicon, silicon carbide, silicon germanium, germanium, a group III-V compound, or a group II-VI compound.

24. The semiconductor structure of claim 22 wherein the insulator substrate is quartz or sapphire.

25. The semiconductor structure of claim 22 wherein the polymer substrate is a polyethylene terephthalate (PET) film.

26. The semiconductor structure of claim 22 wherein the layered substrate is SiO 2 /Si, HfO 2 /Si, Al 2 O 3 /Si, or SOI (silicon on insulator).