Formation of embedded stressor through ion implantation
An extremely-thin silicon-on-insulator transistor includes a buried oxide layer above a substrate. The buried oxide layer, for example, has a thickness that is less than 50 nm. A silicon layer is above the buried oxide layer. A gate stack is on the silicon layer includes at least a gate dielectric formed on the silicon layer and a gate conductor formed on the gate dielectric. A gate spacer has a first part on the silicon layer and a second part adjacent to the gate stack. A first raised source/drain region and a second raised source/drain region each have a first part that includes a portion of the silicon layer and a second part adjacent to the gate spacer. At least one embedded stressor is formed at least partially within the substrate that imparts a predetermined stress on a silicon channel region formed within the silicon layer.
1. A method for fabricating an extremely-thin-silicon-on-insulator transistor, the method comprising:
forming a buried oxide layer on a silicon substrate;
forming a silicon layer on the buried oxide layer;
forming a gate stack on the silicon layer that is above the buried oxide layer;
forming a gate spacer on the silicon layer and on sidewalls of the gate stack;
epitaxially forming a first raised source/drain region and a second raised source/drain region each adjacent to the gate spacer; and
forming at least one embedded stressor at least partially within the substrate that imparts a predetermined stress on a silicon channel region formed within the silicon layer, wherein the at least one embedded stressor is substantially aligned with at least one of the gate stack, and one or more of the first and second raised source/drain regions.
2. The method of claim 1 , wherein the at least one embedded stressor is formed after the gate stack is formed with a gate dielectric on the silicon layer and a gate conductor on the gate dielectric, and prior to forming the first and second raised source/drain regions, wherein forming the at least one embedded stressor comprises:
forming at least one amorphized implant region at least partially within the substrate, wherein the at least one amorphized implant region comprises one of implanted germanium, implanted tin, and implanted carbon; and
recrystallizing the one of implanted germanium, implanted tin, and implanted carbon of the at least one amorphized implant region, the recrystallizing forming one of a silicon-germanium alloy, silicon-tin, or silicon-germanium-tin and a silicon-carbon alloy, respectively.
3. The method of claim 2 , wherein the at least one amorphized implant region is formed by one of a vertical implantation process and an angled implantation process.
4. The method of claim 1 , wherein the gate stack is a replacement gate stack, and wherein forming the at least one embedded stressor comprises:
forming a dielectric layer on the first and second raised source/drain regions, the gate spacer, and the replacement gate stack;
removing the replacement gate stack exposing a portion of a top surface of the silicon layer between a first vertical wall and a second vertical wall of the gate spacer;
implanting one of germanium, tin, and carbon at least partially within the substrate through the portion of the top surface of the silicon layer, the implanting forming at least one amorphized implant region at least partially within the substrate comprising the one of germanium, tin, and carbon; and
recrystallizing the one of germanium, tin, and carbon that has been implanted at least partially within the substrate, the recrystallizing forming one of a silicon-germanium alloy, silicon-tin, or silicon-germanium-tin and a silicon-carbon alloy, respectively.
5. The method of claim 1 , further comprising:
masking at least a gate stack and a silicon layer formed on the buried oxide layer of a corresponding transistor device as the at least one embedded stressor is being formed.
6. The method of claim 1 , wherein the buried oxide layer is formed with a thickness that is less than 50 nm.
7. The method of claim 1 , wherein the silicon layer is formed with a thickness ranging from 2 nm-15 nm.
8. The method of claim 1 , wherein the at least one embedded stressor comprises a first embedded stressor substantially aligned with the first raised source/drain region and a second embedded stressor substantially aligned with the second raised source/drain region.
9. The method of claim 1 , wherein the at least one embedded stressor is substantially aligned with the gate stack.