Film stack including metal hardmask layer for sidewall image transfer fin field effect transistor formation

1. A method for formation of a fin field effect transistor (FinFET) device, the method comprising:

forming a mandrel mask on a metal hardmask layer of a film stack, the film stack including a silicon on insulator (SOI) layer located underneath the metal hardmask layer;

forming a large feature (FX) mask on the metal hardmask layer after formation of the mandrel mask;

etching the mandrel mask and the FX mask simultaneously into the metal hardmask layer;

etching the mandrel mask and the FX mask into the SOI layer using the etched metal hardmask layer as a mask.

2. The method of claim 1 , further comprising forming a cut mask on the metal hardmask layer before etching the mandrel mask and the FX mask into the metal hardmask layer, wherein the cut mask is configured to remove a portion of the mandrel mask or the FX mask corresponding to an unnecessary feature.

3. The method of claim 1 , wherein the metal hardmask layer comprises titanium nitride (TiN).

4. The method of claim 1 , wherein the mandrel mask and the FX mask are formed with stitching.

5. The method of claim 1 , wherein the mandrel mask and the FX mask are formed without stitching.

6. The method of claim 1 , wherein forming the mandrel mask comprises:

forming a plurality of mandrels on the metal hardmask layer;

depositing a sidewall image transfer (SIT) spacer layer over the plurality of mandrels and on the metal hardmask layer;

performing etchback of the SIT spacer layer to expose top surfaces of the plurality of mandrels; and

removing the plurality of mandrels, wherein a portion of the SIT spacer layer that remains on the metal hardmask layer comprises the mandrel mask.

7. The method of claim 6 , wherein the SIT spacer layer comprises one of silicon oxide and silicon nitride, and is deposited by conformal deposition.

8. The method of claim 6 , wherein the FX mask is formed on the metal hardmask layer after the plurality of mandrels are removed.

9. The method of claim 6 , wherein the FX mask is formed on the SIT spacer layer before etchback of the SIT spacer layer is performed such that a portion of the SIT spacer layer comprises the FX mask.

10. The method of claim 1 , wherein the etched metal hardmask layer is removed during etching of the mandrel mask and the FX mask into the SOI layer.

11. The method of claim 10 , further comprising forming a cut mask over the etched SOI layer after etching the mandrel mask and the FX mask into the SOI layer, wherein the cut mask is configured to remove an unnecessary feature formed by the mandrel mask or the FX mask in the SOI layer.

12. The method of claim 1 , wherein the film stack further comprises:

a buried oxide (BOX) layer located underneath the SOI layer;

a thermal silicon oxide layer located on top of the SOI layer;

an amorphous carbon layer located on top of the thermal silicon oxide layer and underneath the metal hardmask layer.

13. The method of claim 12 , wherein the mandrel mask and the FX mask are etched into the amorphous carbon layer and the thermal silicon oxide layer using the etched metal hardmask layer as a mask before etching the mandrel mask and the FX mask into the SOI layer.

14. The method of claim 13 , further comprising removing the amorphous carbon layer after etching the mandrel mask and the FX mask into the SOI layer.

15. A film stack for formation of a fin field effect transistor (FinFET) device, comprising:

a buried oxide (BOX) layer;

a silicon on insulator (SOI) layer located on the BOX layer;

a thermal silicon oxide layer located on top of and in direct contact with the SOI layer;

an amorphous carbon layer located on top of the thermal silicon oxide layer; and

a metal hardmask layer located on top of the amorphous carbon layer.

16. The film stack of claim 15 , wherein the metal hardmask layer comprises titanium nitride (TiN).

17. The film stack of claim 15 , wherein a mandrel mask and a large feature (FX) mask are etched into the metal hardmask layer, and wherein the etched metal hardmask layer is configured to be used as a mask to etch the mandrel mask and the FX mask into the SOI layer.

18. The film stack of claim 15 , further comprising a plurality of mandrels corresponding to a mandrel mask located on the metal hardmask layer.

19. The film stack of claim 18 , further comprising a sidewall image transfer (SIT) spacer layer located over the plurality of mandrels and the metal hardmask layer.

20. The film stack of claim 19 , wherein the SIT spacer layer comprises one of silicon oxide and silicon nitride.