V-groove source/drain MOSFET and process for fabricating same
A method includes providing a substrate containing at least first and second adjacent gate structures on a silicon surface of the substrate; etching a V-shaped groove through the silicon surface between the first and second adjacent gate structures, where the V-shaped groove extends substantially from an edge of the first gate structure to an opposing edge of the second gate structure; implanting a source/drain region into the V-shaped groove; and siliciding the implanted source/drain region. The etching step is preferably performed by using a HCl-based chemical vapor etch (CVE) that stops on a Si(111) plane of the silicon substrate (e.g., a SOI layer). A structure containing FETs that is fabricated in accordance with the method is also disclosed.
1. A method to fabricate transistor devices, comprising:
providing a substrate containing at least first and second adjacent gate structures on a silicon surface of the substrate;
etching a V-shaped groove through the silicon surface between the first and second adjacent gate structures, where the V-shaped groove extends substantially from an edge of the first gate structure to an opposing edge of the second gate structure;
implanting a source/drain region into the V-shaped groove;
and siliciding the implanted source/drain region;
where the substrate is comprised of a silicon on insulator (SOI) layer disposed upon an insulating layer, and where the source/drain region is implanted so as to extend at least from a bottom of the V-shaped groove to the insulating layer.
2. The method of claim 1 , where etching comprises performing a chemical vapor etch.
3. The method of claim 1 , where a surface of the SOI layer is a Si(100) plane, and where a channel direction beneath the gate structures is in a Si(110) plane.
4. The method of claim 1 , where a pitch of the gate structures is in a range of about 40 nm to about 130 nm, and where a spacing between the edge of the first gate structure to the opposing edge of the second gate structure is in a range of about 30 nm to about 50 nm.
5. The method of claim 1 , where siliciding the implanted source/drain region also silicides a top portion of each gate structure.
6. The method of claim 1 , where etching comprises performing a chemical vapor etch (CVE) that stops on a Si(111) plane of the SOI layer.
7. The method of claim 6 , where the CVE is performed using HCl only at about 850° C. at 10 Torr for several minutes.
8. The method of claim 6 , where the CVE is performed using a mixture of HCl and germane (GeH 4 ) at about 550° C. at 40 Torr for several minutes in a flow of H 2 .
9. The method of claim 8 , where there is about a 5:1 ratio HCl:GeH 4 .
10. A method to fabricate transistor devices, comprising:
providing a substrate containing at least first and second adjacent gate structures on a silicon surface of the substrate, the substrate comprising a silicon on insulator (SOI) layer disposed upon an insulating layer;
etching a V-shaped groove through the silicon surface between the first and second adjacent gate structures, where the V-shaped groove extends substantially from an edge of the first gate structure to an opposing edge of the second gate structure and stops on a Si(111) plane of the SOI layer;
implanting a source/drain region into the V-shaped groove so as to extend at least from a bottom of the V-shaped groove to the insulating layer; and
siliciding at least the implanted source/drain region.
11. The method of claim 10 , where etching comprises performing a chemical vapor etch (CVE) using HCl.
12. The method of claim 11 , where the CVE uses one of HCl only at about 850° C. at 10 Torr or a mixture of HCl and germane (GeH 4 ) with about a 5:1 ratio HCl:GeH 4 at about 550° C. at 40 Torr in a flow of gas.