Method and structure for forming high-K/metal gate extremely thin semiconductor on insulator device

1. A method of forming a semiconductor device comprising:

forming a dummy gate on a substrate, the dummy gate having sidewalls with an undercut region present therein;

forming a spacer adjacent to the sidewalls of the dummy gate, wherein the spacer includes a first spacer portion including an extension portion with a first width that fills the undercut region in the sidewall of the dummy gate, and a second spacer portion that is present atop the first spacer portion, the second spacer portion having a second width that is less than the first width;

forming a raised source region and a raised drain region, wherein the raised source region and the raised drain region are separated from the dummy gate by the extension portion of the spacer;

removing the dummy gate to provide an opening to the substrate; and

filling the opening with a gate structure including a gate conductor having an undercut region filled with the extension portion of the spacer.

2. The method of claim 1 , wherein the substrate comprises a semiconductor layer having a thickness of less than 10 nm over a dielectric layer.

3. The method of claim 1 , wherein the forming of the dummy gate comprises:

forming a material stack on the substrate, the material stack comprising a first material layer present on the substrate and a second material layer present on the first material layer; and isotropically etching the first material layer selective to the second material layer to provide the undercut region.

4. The method of claim 1 , wherein forming the spacer comprises depositing a dielectric layer over the dummy gate, and etching the dielectric layer, wherein a remaining portion of the dielectric layer provides the spacer and is present along an entire sidewall of the dummy gate.

5. The method of claim 1 , wherein the forming of the raised source region and the raised drain region comprises epitaxial growth of a semiconductor material on a portion of the substrate adjacent to the spacer, and doping the semiconductor material with a p-type or n-type dopant by ion implantation.

6. The method of claim 1 , wherein the forming of the raised source region and the raised drain region comprises epitaxial growth of a semiconductor material on a portion of the substrate adjacent to the spacers, wherein the semiconductor material is in-situ doped with an n-type or p-type dopant.

7. The method of claim 1 further comprising forming extension regions in the substrate using ion implantation prior to the formation of the raised source region and the raised drain region.

8. The method of claim 1 further comprising diffusing n-type or p-type dopants from the raised source region and the raised drain region into the substrate to provide extension regions.

9. The method of claim 1 , further comprising forming an interlevel dielectric layer over the raised source region, the raised drain region and the dummy gate, and planarizing the interlevel dielectric layer to provide an upper surface of the interlevel dielectric layer that is coplanar with an upper surface of the dummy gate.

10. The method of claim 9 , wherein the removing of the dummy gate comprises removing the dummy gate with an etch process that is selective to the spacer, the interlevel dielectric layer and the substrate.

11. The method of claim 1 , wherein the opening has a base width ranging from 15 nm to 50 nm and the opening has an upper width ranging from 25 nm to 60 nm.

12. The method of claim 1 , wherein the forming of the gate structure comprises forming a conformal gate dielectric on an exposed portion of the substrate within the opening and interior sidewalls of the opening, and depositing a gate conductor on the conformal gate dielectric.

13. The method of claim 12 , wherein the conformal gate dielectric is comprised of a high-k material, and the gate conductor is comprised of a metal.