Extremely thin semiconductor-on-insulator (ETSOI) integrated circuit with on-chip resistors and method of forming the same
An electrical device is provided that in one embodiment includes a semiconductor-on-insulator (SOI) substrate having a semiconductor layer with a thickness of less than 10 nm. A semiconductor device having a raised source region and a raised drain region of a single crystal semiconductor material of a first conductivity is present on a first surface of the semiconductor layer. A resistor composed of the single crystal semiconductor material of the first conductivity is present on a second surface of the semiconductor layer. A method of forming the aforementioned electrical device is also provided.
1. An electrical device comprising:
a semiconductor-on-insulator (SOI) substrate comprising a semiconductor layer with a thickness of less than 10 nm;
a semiconductor device having a raised source region and a raised drain region of a single crystal semiconductor material of a first conductivity present on a first surface of the semiconductor layer; and
a semiconductor-containing resistor comprised of the single crystal semiconductor material of the first conductivity present on a second surface of the semiconductor layer, wherein an upper surface of the single crystal semiconductor material is coplanar with an upper surface of the raised source region and the raised drain region.
2. The electrical device of claim 1 , wherein the semiconductor layer of the SOI substrate is present on a buried insulating layer.
3. The electrical device of claim 2 , wherein the semiconductor device further comprises an extension source region and an extension drain region present in the semiconductor layer and in direct contact with the raised source region and the raised drain region.
4. The electrical device of claim 2 , wherein the semiconductor device is separated from the semiconductor-containing resistor by an isolation region positioned between the semiconductor device and the semiconductor-containing resistor, wherein the isolation region extends through the semiconductor layer into contact with the buried insulating layer.
5. The electrical device of claim 1 , wherein the semiconductor layer is a material selected from the group consisting of Si, strained Si, SiC, SiGe, SiGeC, Si alloys, Ge, Ge alloys, GaAs, InAs, InP, and a combination thereof.
6. The electrical device of claim 1 , wherein the semiconductor device further comprises a gate structure that is present between the raised source region and the raised drain region.
7. The electrical device of claim 1 , wherein the first conductivity is provided by p-type or n-type dopants.
8. The electrical device of claim 1 , wherein the single crystal semiconductor material is a composition selected from the group consisting of silicon, silicon germanium, silicon doped with carbon (Si:C) and a combination thereof.
9. An electrical device comprising:
a semiconductor-on-insulator (SOI) substrate comprising a semiconductor layer with a thickness of less than 10 nm;
a semiconductor device having a raised source region and a raised drain region of a single crystal semiconductor material of a first conductivity present on a first surface of the semiconductor layer; and
a semiconductor-containing resistor comprised of the single crystal semiconductor material of the first conductivity present on a second surface of the semiconductor layer, wherein an upper surface of the single crystal semiconductor material is coplanar with an upper surface of the raised source region and the raised drain region, wherein the semiconductor-containing resistor further comprises metal semiconductor alloy contacts on opposing sides of the upper surface of the single crystal semiconductor material, wherein the metal semiconductor alloy contacts are separated by a dielectric layer that is present on the upper surface of the single crystal semiconductor material, the dielectric layer extending from one metal semiconductor alloy contact on one side of the single crystal semiconductor material to a second metal semiconductor alloy contact on a second opposite side of the single crystal semiconductor material.
10. An electrical device comprising:
a semiconductor-on-insulator (SOI) substrate having a first device region and a second device region, wherein the SOI substrate comprises a semiconductor layer with a thickness of less than 10 nm;
a first conductivity semiconductor device and a first conductivity semiconductor-containing resistor present in the first device region of the SOI substrate, the first conductivity semiconductor device comprising a first raised source region and a first raised drain region of a single crystal semiconductor material, and the first conductivity semiconductor-containing resistor is comprised of the single crystal semiconductor material, wherein an upper surface of a first resistor body of the single crystal semiconductor material for the first conductivity semiconductor-containing resistor is coplanar with an upper surface of the first raised source region and the first raised drain region; and
a second conductivity semiconductor device and a second conductivity semiconductor-containing resistor present in the second device region of the SOI substrate, the second conductivity semiconductor device comprising a second raised source region and a second raised drain region comprised of the single crystal semiconductor material, and the second conductivity semiconductor-containing resistor is comprised of the single crystal semiconductor material, wherein an upper surface of a second resistor body of the single crystal semiconductor material for the second conductivity semiconductor-containing resistor is coplanar with an upper surface of the second raised source region and the second raised drain region.
11. The electric device of claim 10 , wherein the first conductivity is p-type doped, and the second conductivity is n-type doped.
12. The electrical device of claim 10 , wherein the semiconductor layer of the SOI substrate is present on a buried insulating layer.
13. The electrical device of claim 10 , wherein the first conductivity semiconductor device further comprises a first gate structure that is present between the first raised source region and the first raised drain region, and the second conductivity semiconductor device further comprises a second gate structure that is present between the second raised source region and the second raised drain region.
14. The electrical device of claim 13 , wherein the first conductivity semiconductor device further comprises a first extension source region and a first extension drain region present in the semiconductor layer and in direct contact with the first raised source region and the first raised drain region, and the second conductivity semiconductor device further comprises a second extension source region and a second extension drain region present in the semiconductor layer and in direct contact with the second raised source region and the second raised drain region.
15. The electrical device of claim 10 , wherein at least one of the first conductivity semiconductor-containing resistor and the second conductivity semiconductor-containing resistor further comprise metal semiconductor alloy contacts on opposing sides of the upper surface of the single crystal semiconductor material, wherein the metal semiconductor alloy contacts are separated by a dielectric layer that is present on the upper surface of the single crystal semiconductor material.
16. The electrical device of claim 10 , wherein the single crystal semiconductor material is a composition selected from the group consisting of silicon, silicon germanium, silicon doped with carbon (Si:C) and a combination thereof.
17. The electrical device of claim 10 , wherein the semiconductor layer is a material selected from the group consisting of Si, strained Si, SiC, SiGe, SiGeC, Si alloys, Ge, Ge alloys, GaAs, InAs, InP, and a combination thereof.
18. The electrical device of claim 10 , wherein the semiconductor layer has a thickness of less than 5 nm.