Replacement gate CMOS
View Patent ↗A CMOS structure and a method for fabricating the CMOS structure include within a semiconductor substrate a first gate located over a first active region of a first polarity and a second gate located over a second active region of a second polarity different than the first polarity. The first active region and the second active region are separated by an isolation region. The first gate and the second gate are co-linear, with facing endwalls that terminate over the isolation region. The facing endwalls do not have a spacer located or formed adjacent or adjoining thereto, although sidewalls of the first gate and the second gate do. The CMOS structure may be fabricated using a sequential replacement gate method.
1. A complementary metal oxide semiconductor (CMOS) structure comprising:
a first FET having a first polarity located upon a first active region of a semiconductor substrate, said first FET including a first gate that is located upon a first gate dielectric portion, said first gate dielectric portion is located only upon an upper horizontal surface of said semiconductor substrate in the first active region;
a second FET having a second polarity different than the first polarity located upon a second active region of the semiconductor substrate separated from the first active region of the semiconductor substrate by an isolation region, said second FET including a second gate that is located upon a second gate dielectric portion, said second gate dielectric portion is located only upon another upper horizontal surface of said semiconductor substrate in the second active region, wherein:
a third gate dielectric portion is located atop the isolation region and is positioned between and in direct contact with the first and the second gate dielectric portions;
the first gate and the second gate are co-linear;
an endwall of the first gate and an endwall of the second gate terminate facing each other over the isolation region and are entirely bare; and
a spacer is present adjacent or adjoining a sidewall of the first gate and a sidewall of the second gate.
2. The CMOS structure of claim 1 wherein the semiconductor substrate includes a bulk semiconductor substrate.
3. The CMOS structure of claim 1 wherein the semiconductor substrate includes a semiconductor-on-insulator substrate.
4. The CMOS structure of claim 1 wherein the semiconductor substrate includes a hybrid orientation substrate.
5. The CMOS structure of claim 1 where first polarity is a p polarity and second polarity is an n polarity.
6. The CMOS structure of claim 1 wherein the first gate and the second gate comprise the same gate conductor material.
7. The CMOS structure of claim 1 wherein the first gate and the second gate comprise different gate conductor materials.
8. The CMOS structure of claim 1 wherein the first gate dielectric portion and the second gate dielectric portion comprise the same gate dielectric material.
9. The CMOS structure of claim 1 wherein the first gate dielectric portion and the second gate dielectric portion comprise different gate dielectric materials.
10. The CMOS structure of claim 1 wherein the third gate dielectric portion comprises a different gate dielectric material than the first gate dielectric portion or the second gate dielectric portion.
11. A complementary metal oxide semiconductor (CMOS) structure comprising:
a first FET having a first polarity located upon a first active region of a semiconductor substrate, said first FET including a first gate that is located upon a first gate dielectric portion, said first gate dielectric portion is located only upon an upper horizontal surface of said semiconductor substrate in the first active region;
a second FET having a second polarity different than the first polarity located upon a second active region of the semiconductor substrate separated from the first active region of the semiconductor substrate by an isolation region, said second FET including a second gate that is located upon a second gate dielectric portion, said second gate dielectric portion is located only upon another upper horizontal surface of said semiconductor substrate in the second active region, wherein:
a third gate dielectric portion is located atop the isolation region and is positioned between and in direct contact with the first and second gate dielectric portions;
the first gate and the second gate are co-linear;
an endwall of the first gate and an endwall of the second gate terminate facing each other over the isolation region and are separated by a gap, absent a spacer adjacent or adjoining the facing endwall of the first gate or the facing endwall of the second gate, but including a spacer adjacent or adjoining a sidewall of the first gate and a sidewall of the second gate; and
a multi-planar T shaped dielectric material passivation layer passivating the first FET and the second FET, and filling the gap.
12. The CMOS structure of claim 1 where the first polarity is an n polarity and the second polarity is a p polarity.