Method and apparatus for performing model-based OPC for pattern decomposed features
A method for decomposing a target circuit pattern containing features to be imaged into multiple patterns. The process includes the steps of separating the features to be printed into a first pattern and a second pattern; performing a first optical proximity correction process on the first pattern and the second pattern; determining an imaging performance of the first pattern and the second pattern; determining a first error between the first pattern and the imaging performance of the first pattern, and a second error between the second pattern and the imaging performance of said second pattern; utilizing the first error to adjust the first pattern to generate a modified first pattern; utilizing the second error to adjust the second pattern to generate a modified second pattern; and applying a second optical proximity correction process to the modified first pattern and the modified second pattern.
1. A computer-implemented method of performing optical proximity correction (OPC) of target circuit patterns that are decomposed into multiple sub-patterns, the multiple sub-patterns being configured to be imaged using a multiple patterning lithography process, the method comprising:
applying OPC parameters to each sub-pattern;
using feature geometries of the target circuit patterns and Boolean operations to extract overlap areas for each sub-pattern;
determining printing contour errors in the overlap areas with respect to intended target circuit patterns;
using Boolean operations to convert the determined printing contour errors into polygons that are added to the overlap areas, thereby generating modified sub-patterns; and
combining the modified sub-patterns to obtain an improved layout of the target circuit patterns.
2. The method of claim 1 , wherein prior to combining the modified sub-patterns, applying a further round of OPC parameters to the modified sub-patterns.
3. The method of claim 2 , wherein the method further comprises:
verifying that the improved layout of the target circuit pattern produces an improved printing contour when imaged using a simulated model of the multiple patterning lithography process.
4. The method of claim 3 , wherein the step of verifying comprises verifying that an average intensity modulation in the overlap areas is substantially flat.
5. The method of claim 1 , wherein one or more steps of the method are repeated until the improved printing contour matches a desired printing contour.
6. The method of claim 5 , wherein the OPC parameters and the further round of OPC parameters are dynamically updated.
7. The method of claim 1 , wherein initial OPC parameters comprise reference OPC parameters associated with a baseline imaging performance.
8. The method of claim 7 , wherein the OPC parameters include scatter bars as assist patterns that improve imaging performance.
9. The method of claim 1 , wherein the target circuit patterns are decomposed using a coloring line (CLN) method.
10. The method of claim 1 , wherein the target circuit patterns are decomposed using a coloring space (CSP) method.
11. The method of claim 1 , wherein the target circuit patterns represent a full chip layout or a portion thereof.
12. A non-transitory computer-readable storage medium storing a computer program having computer-executable instructions for causing a computer to perform the steps of the method in claim 1 .