3D integrated circuits structure
A structure of connecting at least two integrated circuits in a 3D arrangement by a metal-filled through silicon via which simultaneously connects a connection pad in a first integrated circuit and a connection pad in a second integrated circuit.
1. A 3D integrated circuit comprising:
a first integrated circuit having a connection pad mechanically and electrically joined to a second integrated circuit having a connection pad and a single metal-filled via making simultaneous connection with the first integrated circuit connection pad and the second integrated circuit connection pad wherein the single via within the first integrated circuit has a center portion, two ends and a width within the first integrated circuit which is narrower in the center portion than at the two ends and wherein one of the ends of the single via has a first thickness portion and a second thickness portion such that the second thickness portion is greater in thickness than the first thickness portion and the second thickness portion of the one of the ends of the single via has a surface facing the second integrated circuit such that the surface facing the second integrated circuit makes direct contact with the connection pad in the first integrated circuit.
2. The 3D integrated circuit of claim 1 wherein each of the first integrated circuit and second integrated circuit has a first side having a back end of the line (BEOL) wiring and the first side of the first integrated circuit is directly joined to the first side of the second integrated circuit.
3. The 3D integrated circuit of claim 2 wherein each of the first and second integrated circuits has a second side and the single via extends entirely through the first integrated circuit from the second side of the first integrated circuit through the first integrated circuit and into the BEOL of the second integrated circuit.
4. The 3D integrated circuit of claim 3 further comprising an insulative spacer between the single via and the first integrated circuit.
5. A 3D integrated circuit comprising:
a first semiconductor wafer having a back end of the line (BEOL) wiring on a first side of the first semiconductor wafer and at least one connection pad in the BEOL wiring;
a second semiconductor wafer having a BEOL wiring on a first side of the second semiconductor wafer and at least one landing pad in the BEOL wiring, the first side of the second semiconductor wafer directly joined to the first side of the first semiconductor wafer such that the at least one connection pad is aligned with the at least one landing pad; and
a single metal-filled via in and extending entirely through the first semiconductor wafer to the second semiconductor wafer and having an end portion to simultaneously connect the at least one connection pad and the at least one landing pad, the end portion of the single metal-filled via having a first thickness portion and a second thickness portion such that the second thickness portion is greater in thickness than the first thickness portion and the second thickness portion of the single metal-filled via having a surface facing the second semiconductor wafer such that the surface facing the second semiconductor wafer makes direct contact with the connection pad in the first integrated circuit.
6. The 3D integrated circuit of claim 5 wherein the BEOL of the first semiconductor wafer is joined to the BEOL of the second semiconductor wafer.
7. The 3D integrated circuit of claim 5 further comprising an insulative spacer between the metal-filled via and the first semiconductor wafer.
8. The 3D integrated circuit of claim 5 wherein the metal-filled via within the first semiconductor wafer has a center portion, two ends and a width within the first semiconductor wafer which is narrower in the center portion than in the two ends.
9. A 3D integrated circuit comprising:
a first semiconductor wafer having semiconductor devices and a back end of the line (BEOL) wiring on a first side of the semiconductor wafer and at least one connection pad in the BEOL wiring;
a second semiconductor wafer having BEOL wiring on a first side of the semiconductor wafer and at least one landing pad in the BEOL wiring, the first side of the second semiconductor wafer directly joined to the first side of the first semiconductor wafer such that the at least one connection pad is aligned with the at least one landing pad;
a single metal-filled via in and extending entirely through the first semiconductor wafer and into and stopping on the BEOL wiring of the second semiconductor wafer and having an end portion to simultaneously connect the at least one connection pad and the at least one landing pad, the end portion of the single metal-filled via having a first thickness portion and a second thickness portion such that the second thickness portion is greater in thickness than the first thickness portion and the second thickness portion of the single metal-filled via having a surface facing the second semiconductor wafer such that the surface facing the second semiconductor wafer makes direct contact with the connection pad in the first integrated circuit; and
an insulative spacer between the metal-filled via and the first semiconductor wafer.
10. The 3D integrated circuit of claim 9 wherein the metal-filled via within the first semiconductor wafer has a center portion, two ends and a width within the first semiconductor wafer which is narrower in the center portion than in the two ends.
11. The 3D integrated circuit of claim 9 further comprising a layer of insulator on the BEOL wiring of the first semiconductor wafer and a layer of insulator on the BEOL wiring of the second semiconductor wafer such that the second semiconductor wafer is directly joined to the first semiconductor wafer through the layers of insulator on the second semiconductor wafer and first semiconductor wafer.