IP Library › Granted Patent US 8,705,307
Granted Patent B2
US 8,705,307 · App. 13/298,587 · Granted Apr 22, 2014

Memory system with dynamic refreshing

Inventors: Joab D. Henderson (Pflugerville, TX); Hillery C. Hunter (Chappaqua, NY); Warren E. Maule (Cedar Park, TX); Jeffrey A. Stuecheli (Austin, TX)
Assignee: International Business Machines Corporation
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Quick Facts
Patent No.
US 8,705,307
App. No.
13/298,587
Granted
Apr 22, 2014
Kind
B2
Abstract

An embodiment provided is a memory system with dynamic refreshing that includes a memory device with memory cells. The system also includes a refresh module in communication with the memory device and with a memory controller, the refresh module configured for receiving a refresh command from the memory controller and for refreshing a number of the memory cells in the memory device in response to receiving the refresh command. The number of memory cells refreshed in response to receiving the refresh command is responsive to at least one of a desired bandwidth characteristic and a desired latency characteristic.

Claims (32)

1. A system comprising:

a memory device comprising memory cells; and

a refresh module in communication with the memory device and with a memory controller, the refresh module configured for receiving a refresh command from the memory controller and for refreshing a number of the memory cells in the memory device in response to receiving the refresh command, the number of memory cells refreshed in response to receiving the refresh command based on a desired latency characteristic,

wherein the number of memory cells refreshed in response to receiving the refresh command comprises a first value when the desired latency characteristic includes a low latency and the number of memory cells comprises a second value when the desired bandwidth characteristic includes a low bandwidth utilization, wherein the first value is less than the second value.

2. The system of claim 1 , wherein a frequency of the memory controller communicating the refresh command to the refresh module is responsive to at least one of a desired bandwidth characteristic and the desired latency characteristic.

3. The system of claim 1 , wherein the refresh module comprises a refresh controller.

4. The system of claim 1 , wherein the number of memory cells refreshed in response to receiving the refresh command is further based on a desired bandwidth characteristic.

5. The system of claim 4 , wherein the desired bandwidth characteristic is based on a determined bandwidth utilization.

6. The system of claim 4 , wherein the desired bandwidth characteristic comprises bandwidth available based on current system bandwidth usage.

7. The system of claim 1 , wherein the memory device is a dynamic random access memory (DRAM) device.

8. The system of claim 1 , wherein the desired latency characteristic is based on application information.

9. A method for refreshing a memory device, the method comprising:

determining at least one of a desired bandwidth characteristic and a desired latency characteristic for the memory device;

determining a number of memory cells in the memory device to refresh responsive to the determined at least one of the desired bandwidth characteristic and the desired latency characteristic;

determining a time interval for refreshing the number of memory cells in the memory device responsive to the determined at least one of the desired bandwidth characteristic and the desired latency characteristic; and

communicating a refresh command to the memory device including the number of memory cells in the memory device to refresh.

10. The method of claim 9 , further comprising transmitting a subsequent refresh command after the time interval.

11. The method of claim 9 , wherein determining the number of memory cells in the memory device to refresh comprises determining a first value when the desired latency characteristic includes low latency and the number of memory cells comprise a second value when the desired bandwidth characteristic includes low bandwidth usage, wherein the first value is less than the second value.

12. The method of claim 11 , wherein determining the time interval for refreshing the number of memory cells in the memory device comprises determining a first time interval when the desired latency characteristic includes a low latency and determining a second time interval when the desired bandwidth characteristic includes a low bandwidth usage, wherein the first time interval is less than the second time interval.

13. The method of claim 9 , wherein the desired bandwidth characteristics comprise bandwidth available based on current system bandwidth usage.

14. The method of claim 9 , wherein the at least one of the desired bandwidth characteristic and the desired latency characteristic are based on application information.

15. A computer program product for refreshing a memory device, the computer program product comprising:

a tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method comprising:

determining at least one of a desired bandwidth characteristic and a desired latency characteristic for the memory device;

determining a number of memory cells in the memory device to refresh responsive to the determined at least one of the desired bandwidth characteristic and the desired latency characteristic;

determining a time interval for refreshing the number of memory cells in the memory device responsive to the determined at least one of the desired bandwidth characteristic and the desired latency characteristic; and

communicating a refresh command to the memory device including the number of memory cells in the memory device to refresh.

16. The computer program product of claim 15 , wherein the method further comprises transmitting a subsequent refresh command after the time interval.

17. The computer program product of claim 15 , wherein determining the number of memory cells in the memory device to refresh comprises determining a first value when the desired latency characteristic includes low latency and the number of memory cells comprise a second value when the desired bandwidth characteristic includes low bandwidth usage, wherein the first value is less than the second value.

18. The computer program product of claim 17 , wherein determining the time interval for refreshing the number of memory cells in the memory device comprises determining a first time interval when the desired latency characteristic includes a low latency and determining a second time interval when the desired bandwidth characteristic includes a low bandwidth usage, wherein the first time interval is less than the second time interval.

19. The computer program product of claim 15 , wherein the desired bandwidth characteristics comprise bandwidth available based on current system bandwidth usage.

20. The computer program product of claim 15 , wherein the at least one of the desired bandwidth characteristic and the desired latency characteristic are based on application information.

Assignments (7)
RELEASE OF SECURITY INTEREST Recorded May 12, 2021
From: WILMINGTON TRUST, NATIONAL ASSOCIATION
To: GLOBALFOUNDRIES U.S. INC.
Reel/Frame 056987/0001 →
RELEASE OF SECURITY INTEREST Recorded Nov 20, 2020
From: WILMINGTON TRUST, NATIONAL ASSOCIATION
To: GLOBALFOUNDRIES INC.
Reel/Frame 054636/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 2, 2020
From: GLOBALFOUNDRIES INC.
To: GLOBALFOUNDRIES U.S. INC.
Reel/Frame 054633/0001 →
SECURITY AGREEMENT Recorded Nov 29, 2018
From: GLOBALFOUNDRIES INC.
To: WILMINGTON TRUST, NATIONAL ASSOCIATION
Reel/Frame 049490/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 5, 2015
From: GLOBALFOUNDRIES U.S. 2 LLC; GLOBALFOUNDRIES U.S. INC.
To: GLOBALFOUNDRIES INC.
Reel/Frame 036779/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 3, 2015
From: INTERNATIONAL BUSINESS MACHINES CORPORATION
To: GLOBALFOUNDRIES U.S. 2 LLC
Reel/Frame 036550/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 17, 2011
From: HENDERSON, JOAB D.; HUNTER, HILLERY C.; MAULE, WARREN E.; STUECHELI, JEFFREY A.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 027244/0145 →
Continuity (1)
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