Method and structure of forming backside through silicon via connections
View Patent ↗A method, and the resulting structure, to make a thinned substrate with backside redistribution wiring connected to through silicon vias of varying height. The method includes thinning a backside of a substrate to expose through silicon vias. Then a thick insulator stack, including an etch stop layer, is deposited and planarized. With a planar insulating surface in place, openings in the insulator stack can be formed by etching. The etch stop layer in the dielectric stack accommodates the differing heights vias. The etch stop is removed and a conductor having a liner is formed in the opening. The method gives a unique structure in which a liner around the bottom of the through silicon via remains in tact. Thus, the liner of the via and a liner of the conductor meet to form a double liner at the via/conductor junction.
1. A method of forming an integrated circuit substrate connected to a conductor, the method comprising:
providing a substrate having a first through silicon via and a second through silicon via within the substrate, wherein the substrate has a backside and the first through silicon via has a first height and the second through silicon via has a second height, the first height greater than the second height;
exposing, through the backside of the substrate, an end of the first through silicon via and an end of the second through silicon via;
forming an insulator over the backside of the substrate, the end of the first through silicon via and the end of the second through silicon via;
forming a first opening and a second opening in the insulator, wherein the first opening exposes a bottom surface and a side of the first through silicon via and the second opening exposes a bottom surface of the second through silicon via; and
forming a first conductor in the first opening and second conductor in the second opening, where in the first conductor contacts the bottom surface and the side of the first through silicon via and the second conductor contacts the bottom surface of the second through silicon via.
2. The method of claim 1 , wherein forming an insulator further comprises forming an etch stop layer adjacent to the backside of the substrate and a dielectric layer adjacent the etch stop layer.
3. The method of claim 2 , wherein the etch stop layer is a dielectric layer containing nitrogen.
4. The method of claim 2 , wherein the dielectric layer is an oxide layer.
5. The method of claim 2 , further comprising planarizing the dielectric layer.
6. The method of claim 2 , wherein forming a first opening and a second opening in the insulator layer includes etching the dielectric layer to the etch stop layer, removing the etch stop layer and exposing the bottom surface and the side of the first through silicon via and the bottom surface of the second through silicon via.
7. The method of claim 1 , wherein exposing bottom surface and a side of the first through silicon via and a bottom surface of the second through silicon via includes removing a via insulator and exposing a via liner.
8. The method of claim 1 , wherein forming a conductor in the first opening and the second opening further comprises forming a conductor liner in contact with said via liner.