Integrated circuit having a replacement gate structure and method for fabricating the same

1. A method for fabricating an integrated circuit, comprising:

forming a temporary gate structure on a semiconductor substrate, the temporary gate structure comprising a temporary gate material disposed between two spacer structures, the spacer structures comprising exposed exterior sidewalls opposite the temporary gate material;

forming a first directional silicon nitride liner overlying the temporary gate structure and the semiconductor substrate, but not along at least a majority portion of the exposed exterior sidewalls of the two spacer structures;

etching the first directional silicon nitride liner overlying the temporary gate structure and the temporary gate material to form a trench between the spacer structures, while leaving the directional silicon nitride liner overlying the semiconductor substrate in place;

forming a replacement metal gate structure in the trench, the replacement metal gate structure comprising a work function material and a conductive material; and

forming a contact adjacent to the replacement metal gate structure.

2. The method of claim 1 , wherein forming the first directional silicon nitride liner comprises forming the first direction silicon nitride liner using GCIB nitride deposition.

3. The method of claim 1 , wherein forming the first directional silicon nitride liner comprises forming the first direction silicon nitride liner using HDP nitride deposition.

4. The method of claim 1 , wherein forming the first directional silicon nitride liner comprises forming the first direction silicon nitride liner using PECVD.

5. The method of claim 1 , further comprising forming an interlayer dielectric over the first directional silicon nitride liner.

6. The method of claim 1 , wherein forming the replacement metal gate structure comprises depositing a work function material comprising one or more of TiN, TaN, TaC, or TiAlN.

7. The method of claim 1 , wherein forming the replacement metal gate structure comprises depositing a conductive material comprising one or more of Al, W, Co, or Cu.

8. A method for fabricating an integrated circuit, comprising:

forming a temporary gate structure on a semiconductor substrate, the temporary gate structure comprising a temporary gate material disposed between two spacer structures;

forming a first directional silicon nitride liner overlying the temporary gate structure and the semiconductor substrate;

etching the first directional silicon nitride liner overlying the temporary gate structure and the temporary gate material to form a trench between the spacer structures, while leaving the directional silicon nitride liner overlying the semiconductor substrate in place;

forming a replacement metal gate structure in the trench, the replacement metal gate structure comprising a work function material and a conductive material;

etching the first directional silicon nitride liner overlying the semiconductor substrate after forming the replacement metal gate structure;

forming a silicide region adjacent the replacement metal gate structure;

forming a second directional silicon nitride liner overlying the replacement metal gate structure and the silicide region; and

forming a contact to the silicide region by etching at least a portion of the second directional silicon nitride liner overlying the silicide region.

9. The method of claim 8 , further comprising forming an interlayer dielectric over the first directional silicon nitride liner.

10. The method of claim 9 , further comprising etching back the interlayer dielectric after forming the replacement metal gate structure.

11. The method of claim 9 , wherein forming the contact to the silicide region further comprises etching at least a portion of the interlayer dielectric.

12. The method of claim 8 , further comprising forming an interlayer dielectric overlying the second directional silicon nitride liner.

13. The method of claim 8 , further comprising:

forming a second temporary gate structure on the semiconductor substrate;

forming the first directional silicon nitride liner overlying the second temporary gate structure;

etching the first directional silicon nitride liner overlying the second temporary gate structure;

replacing the temporary gate structure with a second replacement metal gate structure; and

forming the second direction silicon nitride liner over the second replacement gate structure.

14. The method of claim 13 , wherein forming the silicide region comprises forming the silicide region adjacent the second replacement metal gate structure.

15. The method of claim 14 , wherein forming the contact comprises forming the contact between the first and second replacement gate structures.

16. The method of claim 15 , wherein the first and second replacement gate structures are formed at a pitch that is less than or equal to about 70 nm.

17. The method of claim 8 , wherein forming the contact further comprises etching at least a first portion of the second silicon nitride liner overlying the replacement metal gate structure and leaving at least a second portion of the second silicon nitride liner overlying the replacement metal gate structure in place.

18. The method of claim 8 , wherein forming the temporary gate structure comprises forming two sidewall spacers with a polysilicon temporary gate disposed therebetween.

19. The method of claim 8 , wherein forming the replacement metal gate structure further comprises forming a capping material layer overlying the work function material and the conductive material.