Method and structure for forming on-chip high quality capacitors with ETSOI transistors
An ETSOI transistor and a capacitor are formed respectively in a transistor and capacitor region thereof by etching through an ETSOI and thin BOX layers in a replacement gate HK/MG flow. The capacitor formation is compatible with an ETSOI replacement gate CMOS flow. A low resistance capacitor electrode makes it possible to obtain a high quality capacitor or varactor. The lack of topography during dummy gate patterning are achieved by lithography in combination accompanied with appropriate etch.
1. A method of forming an on-chip semiconductor structure comprising:
forming on an ETSOI layer of an SOI substrate, a first dummy gate in both a transistor region and a second dummy gate in a capacitor region, surrounding each of said dummy gates by spacers;
forming on said ETSOI layer a raised source and drain (RSD), said RSD abutting at said spacers;
removing by etching said first dummy gate from said transistor region, and recessing by etching to remove said ETSOI and a thin BOX layer from said capacitor region, including said second dummy gate; and
depositing a high-K dielectric and a metal gate in said gate in said transistor region, and in said recessed capacitor region.
2. The method of claim 1 , further comprising following said forming said raised source and drain, an interlevel dielectric is deposited and planarized, abutting at said dummy gate.
3. The method of claim 1 , wherein said removing said dummy gates is performed by dry or wet etching.
4. The method of claim 1 further comprising covering said transistor region by a block mask and leaving said capacitor region exposed.
5. The method of claim 4 further comprising removing said bock mask.
6. The method of claim 5 , further comprises using photoresist to remove said block mask using plasma etch to dry strip or a sulfuric peroxide to wet strip.
7. The method of claim 1 , further comprising forming a capacitor using a first electrode formed by a back gate below said thin BOX layer of said SOI substrate; a second electrode formed by said metal gate; and said high-K dielectric forming a capacitor dielectric.
8. The method of claim 1 , further comprising forming contacts to said metal gates, raised source and drain.
9. The method of claim 1 wherein said recessed dummy gate, ETSOI and thin BOX layers expose a heavily doped back gate region.
10. The method of claim 1 wherein said high-k and said metal gate are formed by a replacement high-k and metal gate process.
11. The method of claim 9 wherein said exposing said heavily doped back gate region forms a body of a capacitor, reducing said capacitor body resistance, and wherein said capacitor uses said metal gate and doped raised source and drain as a first and second electrode, and having said high-k gate dielectric as capacitor dielectric.
12. The method of claim 1 wherein said high-K dielectric is made of metal oxide or dielectric materials.
13. The method of claim 1 wherein said spacers are formed by depositing a film or by using a blanket layer deposition and anisotropic etchback.
14. The method of claim 1 wherein said RSD are grown epitaxially, forming an extension.
15. The method of claim 14 , further comprising forming said extension by implantation or by driving dopants from an in-situ doped RSD, said dopants comprising lanthanum or aluminum.