Thick on-chip high-performance wiring structures
Methods for fabricating a back-end-of-line (BEOL) wiring structure, BEOL wiring structures, and design structures for a BEOL wiring structure. The BEOL wiring may be fabricated by forming a first wire in a dielectric layer and annealing the first wire in an oxygen-free atmosphere. After the first wire is annealed, a second wire is formed in vertical alignment with the first wire. A final passivation layer, which is comprised of an organic material such as polyimide, is formed that covers an entirety of a sidewall of the second wire.
1. A method of fabricating a back-end-of-line wiring structure, the method comprising:
forming a first wire and a second wire in a first dielectric layer;
annealing the first wire and the second wire in an oxygen-free atmosphere;
after annealing the first wire and the second wire, forming a third wire that is stacked with the first wire and a fourth wire that is stacked with the second wire; and
forming a final passivation layer comprised of an organic material that covers an entirety of a sidewall of the third wire and of a sidewall of the fourth wire,
wherein the first wire and the second wire each have a thickness ranging from 6 microns to 10 microns, the third wire and the fourth wire each have a thickness ranging from 4 microns to 6 microns, and the second wire is adjacent to the first wire and laterally separated from the first wire by a distance less than or equal to 15 microns.
2. The method of claim 1 wherein forming the first wire and the second wire in the first dielectric layer comprises:
depositing the first dielectric layer;
etching a trench in the first dielectric layer; and
depositing a conductor layer that partially resides in the trench to define the first and second wires and that covers a top surface of the first dielectric layer.
3. The method of claim 2 further comprising:
after annealing, removing the conductor layer from the top surface of the first dielectric layer so that the top surface of the first and second wires is planarized relative to the top surface of the first dielectric layer.
4. The method of claim 3 wherein the conductor layer is removed from the top surface of the first dielectric layer by chemical-mechanical polishing.
5. The method of claim 1 wherein the oxygen-free atmosphere comprises nitrogen gas.
6. The method of claim 1 wherein the first wire and the second wire are annealed at a temperature in a range of 250° C. to 425° C.
7. The method of claim 1 wherein the third wire is formed in direct contact with the first wire, the fourth wire is formed in direct contact with the second wire, the first wire and the second wire are formed by a damascene process, and the third wire and the fourth wire are formed by subtractive etching.
8. The method of claim 1 wherein forming the third wire that is stacked with the first wire and the fourth wire that is stacked with the second wire comprises:
depositing a blanket conductor layer on a top surface of the first dielectric layer, the first wire, and the second wire; and
subtractively etching the conductor layer to define the third wire and the fourth wire.
9. The method of claim 8 wherein the conductor layer is deposited and subtractively etched before the final passivation layer is formed.
10. The method of claim 1 wherein the first and second wires are comprised of a first conductor, and the third and fourth wires are comprised of a second conductor different from the first conductor.
11. The method of claim 1 further comprising:
forming a capping layer on the first dielectric layer,
wherein a portion of the third wire extends through the capping layer to the first wire, and the sidewall of the third wire terminates at a top surface of the capping layer.
12. The method of claim 1 wherein the first wire is comprised of copper, and the third wire is comprised of aluminum.
13. The method of claim 1 wherein the third wire and the fourth wire are comprised of aluminum and less than or equal to 1 percent of copper.
14. The method of claim 13 wherein the first and third wires define a first winding of an inductor, and the second and fourth wires define a second winding of the inductor.
15. The method of claim 1 wherein annealing the first wire and the second wire in the oxygen-free atmosphere comprises:
increasing a grain size of a conductor comprising the first wire and the second wire through recrystallization.
16. The method of claim 1 wherein the first and third wires comprise a first winding of an inductor, and the second and fourth wires comprise a second winding of the inductor.