Rare-earth oxide isolated semiconductor fin
A dielectric template layer is deposited on a substrate. Line trenches are formed within the dielectric template layer by an anisotropic etch that employs a patterned mask layer. The patterned mask layer can be a patterned photoresist layer, or a patterned hard mask layer that is formed by other image transfer methods. A lower portion of each line trench is filled with an epitaxial rare-earth oxide material by a selective rare-earth oxide epitaxy process. An upper portion of each line trench is filled with an epitaxial semiconductor material by a selective semiconductor epitaxy process. The dielectric template layer is recessed to form a dielectric material layer that provides lateral electrical isolation among fin structures, each of which includes a stack of a rare-earth oxide fin portion and a semiconductor fin portion.
1. A semiconductor structure comprising:
a fin structure located on a planar top surface of a substrate, wherein said fin structure comprises a rare-earth oxide fin portion and a semiconductor fin portion in contact with a top surface of said rare-earth oxide fin portion; and
a gate structure including a gate dielectric layer and overlying, and straddling, said fin structure.
2. The semiconductor structure of claim 1 , wherein said rare-earth oxide fin portion comprises a single crystalline rare earth oxide material selected from single crystalline Er 2 O 3 , single crystalline Gd 2 O 3 , single crystalline Nd 2 O 3 , single crystalline Pr 2 O 3 , single crystalline La 2 O 3 , and a single crystalline alloy thereof.
3. The semiconductor structure of claim 1 , wherein said fin structure has a substantially uniform width between a pair of sidewall surfaces.
4. The semiconductor structure of claim 1 , wherein said rare earth-oxide fin portion comprises a single crystalline rare-earth oxide material that is epitaxially aligned to a single crystalline material in said substrate.
5. The semiconductor structure of claim 4 , wherein said semiconductor fin portion comprises a single crystalline semiconductor material that is epitaxially aligned to said single crystalline rare-earth oxide material.
6. The semiconductor structure of claim 5 , wherein said single crystalline semiconductor material is selected from single crystalline silicon, a single crystalline silicon germanium alloy, a single crystalline silicon carbon alloy, a single crystalline silicon germanium carbon alloy, a single crystalline III-V compound semiconductor material, a single crystalline II-VI compound semiconductor material, and an alloy or a combination thereof.
7. The semiconductor structure of claim 4 , wherein said single crystalline material in said substrate is a single crystalline semiconductor material.
8. The semiconductor structure of claim 7 , wherein said substrate is a bulk semiconductor substrate including said single crystalline semiconductor material throughout an entirety thereof.
9. The semiconductor structure of claim 1 , further comprising a dielectric material layer in contact with a top surface of said substrate and having a planar top surface located below a level of an interface between said rare-earth oxide fin portion and said semiconductor fin portion.
10. A semiconductor structure comprising a fin structure located on a planar top surface of a substrate, wherein said fin structure comprises a rare-earth oxide fin portion and a semiconductor fin portion in contact with a top surface of said rare-earth oxide fin portion, wherein said rare earth-oxide fin portion comprises a single crystalline rare-earth oxide material that is epitaxially aligned to a single crystalline material in said substrate.
11. The semiconductor structure of claim 10 , wherein said semiconductor fin portion comprises a single crystalline semiconductor material that is epitaxially aligned to said single crystalline rare-earth oxide material.
12. The semiconductor structure of claim 11 , wherein said single crystalline semiconductor material is selected from single crystalline silicon, a single crystalline silicon germanium alloy, a single crystalline silicon carbon alloy, a single crystalline silicon germanium carbon alloy, a single crystalline III-V compound semiconductor material, a single crystalline II-VI compound semiconductor material, and an alloy or a combination thereof.
13. The semiconductor structure of claim 10 , wherein said single crystalline material in said substrate is a single crystalline semiconductor material.
14. The semiconductor structure of claim 13 , wherein said substrate is a bulk semiconductor substrate including said single crystalline semiconductor material throughout an entirety thereof.
15. A semiconductor structure comprising:
a fin structure located on a planar top surface of a substrate, wherein said fin structure comprises a rare-earth oxide fin portion and a semiconductor fin portion in contact with a top surface of said rare-earth oxide fin portion; and
a dielectric material layer in contact with a top surface of said substrate and having a planar top surface located below a level of an interface between said rare-earth oxide fin portion and said semiconductor fin portion.
16. The semiconductor structure of claim 15 , wherein said dielectric material layer comprises a dielectric material that is not a rare-earth oxide material.
17. The semiconductor structure of claim 15 , further comprising:
a gate dielectric layer contacting sidewalls of said semiconductor fin portion; and
a gate electrode spaced from a top surface and sidewall surfaces of said semiconductor fin portion by said gate dielectric layer.
18. The semiconductor structure of claim 17 , wherein said semiconductor fin portion comprises:
a body region underlying said gate electrode;
a source region located at one end of said semiconductor fin portion; and
a drain region located at another end of said semiconductor fin portion.
19. The semiconductor structure of claim 15 , wherein said gate structure further comprises a gate electrode spaced from a top surface and sidewall surfaces of said semiconductor fin portion by said gate dielectric layer.
20. The semiconductor structure of claim 19 , wherein said semiconductor fin portion comprises:
a body region underlying said gate electrode;
a source region located at one end of said semiconductor fin portion; and
a drain region located at another end of said semiconductor fin portion.