Semiconductor device and method of forming PIP with inner known good die interconnected with conductive bumps
A PiP semiconductor device has an inner known good semiconductor package. In the semiconductor package, a first via is formed in a temporary carrier. A first conductive layer is formed over the carrier and into the first via. The first conductive layer in the first via forms a conductive bump. A first semiconductor die is mounted to the first conductive layer. A first encapsulant is deposited over the first die and carrier. The semiconductor package is mounted to a substrate. A second semiconductor die is mounted to the first conductive layer opposite the first die. A second encapsulant is deposited over the second die and semiconductor package. A second via is formed in the second encapsulant to expose the conductive bump. A second conductive layer is formed over the second encapsulant and into the second via. The second conductive layer is electrically connected to the second die.
1. A semiconductor device, comprising:
a support layer;
a semiconductor package disposed over the support layer, the semiconductor package including,
(a) a first semiconductor die or component,
(b) a first encapsulant deposited over the first semiconductor die or component with an encapsulant bump extending from a body of the first encapsulant, and
(c) a first conductive layer disposed over the first encapsulant including the encapsulant bump to form a conductive bump;
a second encapsulant deposited over a surface of the semiconductor package opposite the support layer, the second encapsulant including an opening over the conductive bump; and
a second conductive layer formed in the opening over the conductive bump.
2. The semiconductor device of claim 1 , further including an interconnect structure formed over the second encapsulant, the interconnect structure being electrically connected to the conductive bump.
3. The semiconductor device of claim 1 , further including a second semiconductor die or component disposed over the semiconductor package.
4. The semiconductor device of claim 1 , wherein the semiconductor package further includes a bond wire formed between the conductive bump and first semiconductor die or component.
5. The semiconductor device of claim 1 , wherein the first semiconductor die or component includes a known good die or component.
6. The semiconductor device of claim 1 , wherein the support layer operates as a substrate, stiffener, heat sink, shielding layer, printed circuit board, or carrier.
7. A semiconductor device, comprising:
a first semiconductor die or component;
a first encapsulant deposited over the first semiconductor die or component with an encapsulant bump extending from a body of the first encapsulant;
a first conductive layer disposed over a first surface of the first encapsulant including the encapsulant bump to form a conductive bump; and
a second encapsulant deposited over and around the first encapsulant, the second encapsulant including a via formed through a surface of the second encapsulant.
8. The semiconductor device of claim 7 , further including a bond wire formed between the conductive bump and first semiconductor die or component.
9. The semiconductor device of claim 7 , further including:
a support layer disposed over a second surface of the first encapsulant opposite the first surface of the first encapsulant;
the second encapsulant deposited over the support layer; and
an interconnect structure formed over the second encapsulant and within the via.
10. The semiconductor device of claim 9 , further including a second semiconductor die or component disposed over the first surface of the first encapsulant.
11. The semiconductor device of claim 9 , wherein the interconnect structure includes:
a second conductive layer formed over the second encapsulant;
an insulating layer formed over the second conductive layer; and
a third conductive layer formed over the second conductive layer.
12. The semiconductor device of claim 9 , wherein the support layer operates as a substrate, stiffener, heat sink, shielding layer, printed circuit board, or carrier.
13. The semiconductor device of claim 7 , wherein the first semiconductor die or component includes a known good die or component.
14. A semiconductor device, comprising:
a support layer; and
a semiconductor package disposed over the support layer, the semiconductor package including,
(a) a first semiconductor die or component,
(b) a first non-conductive encapsulant deposited over the first semiconductor die or component with an encapsulant bump extending from a body of the first non-conductive encapsulant, and
(c) a first conductive layer disposed over a first surface of the first non-conductive encapsulant including the encapsulant bump to form a conductive bump.
15. The semiconductor device of claim 14 , wherein the semiconductor package further includes a bond wire formed between the conductive bump and first semiconductor die or component.
16. The semiconductor device of claim 14 , further including:
a second encapsulant deposited over the support layer and semiconductor package; and
an interconnect structure formed over the second encapsulant.
17. The semiconductor device of claim 16 , wherein the interconnect structure includes:
a second conductive layer formed over the second encapsulant;
an insulating layer formed over the second conductive layer; and
a third conductive layer formed over the second conductive layer.
18. The semiconductor device of claim 14 , further including a second semiconductor die or component disposed over the semiconductor package.
19. The semiconductor device of claim 14 , wherein the support layer operates as a substrate, stiffener, heat sink, shielding layer, printed circuit board, or carrier.
20. The semiconductor device of claim 14 , wherein the first semiconductor die or component includes a known good die or component.
21. A semiconductor device, comprising:
a support layer; and
a semiconductor package disposed over the support layer, the semiconductor package including a bump comprising an inner insulating material and outer conductive material.
22. The semiconductor device of claim 21 , wherein the semiconductor package includes:
a first semiconductor die or component;
an encapsulant deposited over the first semiconductor die or component, wherein a portion of the encapsulant constitutes the inner insulating material of the bump; and
a conductive layer formed over the encapsulant, wherein a portion of the conductive layer constitutes the outer conductive material of the bump.
23. The semiconductor device of claim 21 , further including:
an encapsulant deposited over the support layer and semiconductor package; and
an interconnect structure formed over the encapsulant.
24. The semiconductor device of claim 21 , further including a second semiconductor die or component disposed over the semiconductor package.
25. The semiconductor device of claim 21 , wherein the support layer operates as a substrate, stiffener, heat sink, shielding layer, printed circuit board, or carrier.