Controlling ferroelectricity in dielectric films by process induced uniaxial strain
A method of controlling ferroelectric characteristics of integrated circuit device components includes forming a ferroelectrically controllable dielectric layer over a substrate; and forming a stress exerting structure proximate the ferroelectrically controllable dielectric layer such that a substantially uniaxial strain is induced in the ferroelectrically controllable dielectric layer by the stress exerting structure; wherein the ferroelectrically controllable dielectric layer comprises one or more of: a ferroelectric oxide layer and a normally non-ferroelectric material layer that does not exhibit ferroelectric properties in the absence of an applied stress.
1. A ferroelectric field effect transistor (FET) device, comprising:
a ferroelectrically controllable gate dielectric layer disposed between a gate electrode and a substrate; and
a stress exerting structure formed proximate the ferroelectrically controllable dielectric layer such that a substantially uniaxial strain is induced in the ferroelectrically controllable dielectric layer by the stress exerting structure, the substantially uniaxial strain comprising a strain introduced in one direction of a surface of the ferroelectrically controllable gate dielectric layer;
wherein the ferroelectrically controllable gate dielectric layer comprises one or more of: a ferroelectric oxide layer and a normally non-ferroelectric material layer that does not exhibit ferroelectric properties in the absence of an applied stress.
2. The device of claim 1 , wherein the ferroelectrically controllable gate dielectric layer comprises one or more of: BaTiO 3 , Pb[Zr x Ti 1-x ]O 3 (PZT), SrBi 2 Ta 2 O 9 (SBT), SrTiO 3 (STO), Ba 1-x Sr x TiO 3 (BST), PbTiO 3 , CaMnO 3 and BiFeO 3 .
3. The device of claim 1 , wherein the substrate is a silicon substrate and the stress exerting structure comprises epitaxially grown silicon germanium source and drain regions that induce a compressive uniaxial strain in the ferroelectrically controllable dielectric layer.
4. The device of claim 1 , wherein the substrate is a silicon substrate and the stress exerting structure comprises epitaxially grown carbon doped silicon source and drain regions that induce a tensile uniaxial strain in the ferroelectrically controllable dielectric layer.
5. The device of claim 1 , wherein the stress exerting structure comprises a compressive nitride layer formed over the FET.
6. The device of claim 1 , wherein the stress exerting structure comprises a tensile nitride layer formed over the FET.
7. The device of claim 1 , wherein the gate dielectric layer further comprises one or more additional dielectric layers.
8. A ferroelectric metal-insulator-metal (MIM) capacitor, comprising:
a lower electrode layer formed over a substrate;
a capacitor dielectric layer comprising a ferroelectrically controllable dielectric layer formed over the lower electrode;
an upper electrode layer formed over the ferroelectrically controllable dielectric layer; and
a stress exerting structure formed proximate the ferroelectrically controllable dielectric layer such that a substantially uniaxial strain is induced in the ferroelectrically controllable dielectric layer, the substantially uniaxial strain comprising a strain introduced in one direction of a surface of the ferroelectrically controllable dielectric layer;
wherein the ferroelectrically controllable gate dielectric layer comprises one or more of: a ferroelectric oxide layer and a normally non-ferroelectric material layer that does not exhibit ferroelectric properties in the absence of an applied stress.
9. The device of claim 8 , wherein the ferroelectrically controllable gate dielectric layer comprises one or more of: BaTiO 3 , Pb[Zr x Ti 1-x ]O 3 (PZT), SrBi 2 Ta 2 O 9 (SBT), SrTiO 3 (STO), Ba 1-x Sr x TiO 3 (BST), PbTiO 3 , CaMnO 3 and BiFeO 3 .
10. The device of claim 8 , wherein the stress exerting structure comprises a compressive nitride layer formed over the MIM capacitor.
11. The device of claim 8 , wherein the stress exerting structure comprises a tensile nitride layer formed over the MIM capacitor.
12. The device of claim 8 , wherein the capacitor dielectric layer further comprises one or more additional dielectric layers.
13. A ferroelectric field effect transistor (FET) device, comprising:
a ferroelectrically controllable gate dielectric layer disposed between a gate electrode and a substrate; and
a stress exerting structure formed proximate the ferroelectrically controllable dielectric layer such that a substantially uniaxial strain is induced in the ferroelectrically controllable dielectric layer by the stress exerting structure;
wherein the ferroelectrically controllable gate dielectric layer comprises a normally non-ferroelectric material layer that does not exhibit ferroelectric properties in the absence of an applied stress.
14. The device of claim 13 , wherein the ferroelectrically controllable dielectric layer comprises one or more of: SrTiO 3 and CaMnO 3 .