Accurate control of distance between suspended semiconductor nanowires and substrate surface
A method of forming a semiconductor device is provided. The method includes providing a structure including, a handle substrate, a buried boron nitride layer located above an uppermost surface of the handle substrate, a buried oxide layer located on an uppermost surface of the buried boron nitride layer, and a top semiconductor layer located on an uppermost surface of the buried oxide layer. Next, a first semiconductor pad, a second semiconductor pad and a plurality of semiconductor nanowires connecting the first semiconductor pad and the second semiconductor pad in a ladder-like configuration are patterned into the top semiconductor layer. The semiconductor nanowires are suspended by removing a portion of the buried oxide layer from beneath each semiconductor nanowire, wherein a portion of the uppermost surface of the buried boron nitride layer is exposed. Next, a gate all-around field effect transistor is formed.
1. A method of forming a semiconductor device comprising:
providing a structure comprising, from bottom to top, a handle substrate, a buried boron nitride layer located above an uppermost surface of the handle substrate, a buried oxide layer located on an uppermost surface of the buried boron nitride layer, and a top semiconductor layer located on an uppermost surface of the buried oxide layer;
patterning a first semiconductor pad, a second semiconductor pad and a plurality of semiconductor nanowires connecting the first semiconductor pad and the second semiconductor pad in a ladder configuration into said top semiconductor layer;
suspending each semiconductor nanowire of said plurality of semiconductor nanowires by removing a portion of said buried oxide layer from beneath each semiconductor nanowire, wherein a portion of the uppermost surface of the buried boron nitride layer is exposed;
forming a gate dielectric surrounding each semiconductor nanowire and located directly on a top surface and a bottom surface of each semiconductor nanowires; and
forming a gate surrounding each semiconductor nanowire and located directly on a surface of each gate dielectric, wherein during said forming said gate dielectric a gate dielectric portion is formed directly on a surface of said buried boron nitride layer, and in contact with a surface of said gate located beneath each semiconductor nanowire.
2. The method of claim 1 , wherein said buried boron nitride layer is in direct contact with said uppermost surface of the handle substrate.
3. The method of claim 1 , wherein said structure further includes another buried oxide layer, said another buried oxide layer is positioned between said buried boron nitride layer and said uppermost surface of the handle substrate.
4. The method of claim 1 , further comprising thinning and reshaping each of said semiconductor nanowires after said suspending, and prior to said forming said gate dielectric and said gate.
5. The method of claim 4 , wherein said thinning and reshaping comprises annealing in an inert gas.
6. The method of claim 4 , wherein said thinning and reshaping comprises annealing in hydrogen gas.
7. The method of claim 6 , wherein said annealing is performed at pressure of from 30 torr to 1000 torr, and at a temperature from 600° C. to 1100° C.
8. The method of claim 1 , wherein said top semiconductor layer comprises silicon.
9. The method of claim 1 , wherein a vertical distance between a central portion of each semiconductor nanowire and said uppermost surface of the exposed portion of said buried boron nitride layer is constant.
10. The method of claim 1 , wherein said suspending comprises isotropic etching.
11. The method of claim 10 , wherein said isotropic etching includes contacting with dilute hydrofluoric acid (DHF).
12. The method of claim 1 , wherein said suspending consists essentially of performing an anneal in an inert gas or hydrogen gas.