Programming select gate transistors and memory cells using dynamic verify level
Programming accuracy is increased for select gate transistors and memory cells by using a dynamic verify voltage which increases from an initial level to a final level during a programming operation. Faster-programming transistors are locked out from programming before slower-programming transistors, but experience program disturb which increases their threshold voltage to a common level with the slower-programming transistors at the conclusion of the programming operation. For programming of memory cells to different target data states, an offset between the initial and final verify levels can be different for each data state. In one approach, the offset is greater for lower target data states. The increases in the dynamic verify voltage can be progressively smaller with each subsequent program-verify iteration of the programming operation. The start of the increase can be adapted to the programming progress or can be at a predetermined program-verify iteration.
1. A method for programming transistors in a memory device, comprising:
performing each program-verify iteration of a plurality of program-verify iterations, the plurality of program-verify iterations comprise program-verify iterations for a set of transistors which are to be programmed in a programming operation, each transistor initially has a program status which indicates that the transistor is to be programmed, the performing each program-verify iteration comprises applying a program pulse to the set of transistors, determining whether a threshold voltage of at least some of the transistors with the program status exceeds a lockout verify voltage and changing the program status to a lockout status for a remainder of the programming operation for each of the transistors for which the threshold voltage is determined to exceed the lockout verify voltage, the lockout verify voltage is stepped up in multiple program-verify iterations of the program-verify iterations for the set of transistors.
2. The method of claim 1 , wherein:
the lockout verify voltage is at a fixed initial level in one or more initial program-verify iterations of the program-verify iterations for the set of transistors which are before the multiple program-verify iterations.
3. The method of claim 2 , further comprising:
beginning the multiple program-verify iterations at a predetermined program-verify iteration of the programming operation, after the one or more initial program-verify iterations.
4. The method of claim 2 , further comprising:
adaptively determining during the programming operation, based on a programming progress of the set of transistors, when to begin the multiple program-verify iterations.
5. The method of claim 1 , further comprising:
determining a natural threshold voltage distribution of the set of transistors; and
setting the fixed initial level to be relatively lower when the natural threshold voltage distribution is relatively wider and relatively higher when the natural threshold voltage distribution is relatively narrower.
6. The method of claim 1 , further comprising:
concluding the multiple program-verify iterations and beginning one or more final program-verify iterations of the program-verify iterations for the set of transistors when the lockout verify voltage has been stepped up to a maximum allowed level,
the lockout verify voltage is at the maximum allowed level in the one or more final program-verify iterations.
7. The method of claim 1 , wherein:
the multiple program-verify iterations are consecutive program-verify iterations.
8. The method of claim 1 , further comprising:
during the program pulse of each program-verify iteration of the program-verify iterations for the set of transistors, setting a respective drain voltage at a lockout level for transistors having the lockout status and setting a respective drain voltage at a program level for transistors having the program status.
9. The method of claim 1 , wherein:
for at least some of the transistors, a threshold voltage increases after changing the program status to the lockout status, bringing threshold voltages of faster-programming transistors of the set of transistors closer to threshold voltages of slower-programming transistors of the set of transistors.
10. The method of claim 1 , wherein:
the set of transistors comprises charge-trapping select gate transistors of respective NAND strings.
11. The method of claim 1 , wherein:
the set of transistors comprises memory cell transistors of respective NAND strings.
12. The method of claim 1 , wherein:
the lockout verify voltage in each of the multiple program-verify iterations is stepped up using a fixed step size.
13. The method of claim 1 , wherein:
the lockout verify voltage is stepped up in each of the multiple program-verify iterations by progressively smaller step sizes.
14. The method of claim 1 , wherein:
the set of transistors is one set of transistors among a plurality of sets of transistors;
the one set of transistors is programmed to one target data state in the programming operation;
the lockout verify voltage is for the one target data state;
the plurality of sets of transistors comprises another set of transistors which are programmed to another target data state in the programming operation using another lockout verify voltage which is stepped up in multiple program-verify iterations of the plurality of program-verify iterations, the another target data state is higher than the one target data state; and
the another lockout verify voltage is stepped up in a range of voltages which is less than a range of voltages in which the lockout verify voltage for the one target data state is stepped up.
15. The method of claim 14 , wherein:
the plurality of sets of transistors comprises an additional set of transistors which are programmed to an additional target data state in the programming operation using an additional lockout verify voltage which is stepped up in multiple program-verify iterations of the plurality of program-verify iterations; and
a range of voltages in which the additional lockout verify voltage is stepped up is less than the range of voltages in which the another lockout verify voltage is stepped up.
16. A non-volatile storage system, comprising:
a set of transistors which are to be programmed in a programming operation; and
a control circuit, the control circuit is configured to: perform each program-verify iteration of a plurality of program-verify iterations of the programming operation, the plurality of program-verify iterations comprises program-verify iteration for the set of transistors, each transistor initially has a program status which indicates that the transistor is to be programmed, each program-verify iteration involves application of a program pulse to the set of transistors, a determination of whether a threshold voltage of at least some of the transistors with the program status exceeds a lockout verify voltage and a change of the program status to a lockout status for a remainder of the programming operation for each of the transistors for which the threshold voltage is determined to exceed the lockout verify voltage, the lockout verify voltage is stepped up in multiple program-verify iterations of the program-verify iterations for the set of transistors.
17. The non-volatile storage system of claim 16 , wherein:
the lockout verify voltage is at a fixed initial level in one or more initial program-verify iterations of the program-verify iterations for the set of transistors which are before the multiple program-verify iterations.
18. The non-volatile storage system of claim 16 , wherein:
the control circuit is configured to conclude the multiple program-verify iterations and begin one or more final program-verify iterations of the program-verify iterations for the set of transistors when the lockout verify voltage has been stepped up to a maximum allowed level; and
the lockout verify voltage is the maximum allowed level in the one or more final program-verify iterations.
19. A method for programming memory cells in a memory device, comprising:
performing each program-verify iteration of a plurality of program-verify iterations, the plurality of program-verify iterations comprise program-verify iterations for one set of memory cells which are to be programmed to one target data state using a lockout verify voltage of the one target data state in a programming operation, and program-verify iterations for another set of memory cells which are to be programmed to another target data state using a lockout verify voltage of the another target data state in the programming operation, each memory cell in the one set of memory cells and the another set of memory cells initially has a program status which indicates that the memory cell is to be programmed, the performing each program-verify iteration comprises:
applying a program pulse to the one set of memory cells and the another set of memory cells;
determining whether a threshold voltage of at least some of the memory cells in the one set of memory cells with the program status exceeds the lockout verify voltage of the one target data state and changing the program status to a lockout status for a remainder of the programming operation for each of the memory cells in the one set of memory cells for which the threshold voltage is determined to exceed the lockout verify voltage of the one target data state; and
determining whether a threshold voltage of at least some of the memory cells in the another set of memory cells with the program status exceeds the lockout verify voltage of the another target data state and changing the program status to the lockout status for a remainder of the programming operation for each of the memory cells in the another set of memory cells for which the threshold voltage is determined to exceed the lockout verify voltage of the another target data state, the lockout verify voltage of the one target data state is stepped up in the program-verify iterations for the one set of memory cells at a different rate than a rate at which the lockout verify voltage of the another target data state is stepped up in the program-verify iterations for the another set of memory cells.
20. The method of claim 19 , wherein:
the lockout verify voltage of the one target data state is stepped up in the program-verify iterations for the one set of memory cells by progressively smaller step sizes.
21. The method of claim 19 , wherein:
the program-verify iterations for the one set of memory cells overlap with the program-verify iterations for the another set of memory cells.
22. The method of claim 19 , wherein:
the plurality of program-verify iterations comprise program-verify iterations for an additional set of memory cells which are to be programmed to an additional target data state using a lockout verify voltage of the additional target data state in the programming operation;
each memory cell in the additional set of memory cells initially has the program status; and
the performing each program-verify iteration comprises:
applying the program pulse to the additional set of memory cells; and
determining whether a threshold voltage of at least some of the memory cells in the additional set of memory cells with the program status exceeds the lockout verify voltage of the additional target data state and changing the program status to the lockout status for a remainder of the programming operation for each of the memory cells in the additional set of memory cells for which the threshold voltage is determined to exceed the lockout verify voltage of the additional target data state.
23. The method of claim 22 , wherein:
the lockout verify voltage of the another target data state is stepped up in a range of voltages which is greater than a range of voltages in which the lockout verify voltage for the one target data state is stepped up.
24. The method of claim 23 , wherein:
the lockout verify voltage of the additional target data state is stepped up in the program-verify iterations for the additional set of memory cells in a range of voltages which is less than the range of voltages in which the lockout verify voltage of the another target data state is stepped up in the program-verify iterations for the another set of memory cells.