Silicon controlled rectifier with stress-enhanced adjustable trigger voltage
Device structures, fabrication methods, operating methods, and design structures for a silicon controlled rectifier. The method includes applying a mechanical stress to a region of a silicon controlled rectifier (SCR) at a level sufficient to modulate a trigger current of the SCR. The device and design structures include a SCR with an anode, a cathode, a first region, and a second region of opposite conductivity type to the first region. The first and second regions of the SCR are disposed in a current-carrying path between the anode and cathode of the SCR. A layer is positioned on a top surface of a semiconductor substrate relative to the first region and configured to cause a mechanical stress in the first region of the SCR at a level sufficient to modulate a trigger current of the SCR.
1. A device structure formed using a semiconductor substrate having a top surface, the device structure comprising:
a silicon controlled rectifier (SCR) including an anode, a cathode, a first well in the semiconductor substrate and having a first conductivity type, and a second well in the semiconductor substrate and having a second conductivity type opposite to the first conductivity type, the first well and the second well disposed in a current-carrying path between the anode and the cathode;
a first stress layer on the top surface of the semiconductor substrate, the first stress layer located at a position on the top surface of the semiconductor substrate and configured to cause a first mechanical stress in the first well at a level sufficient to modulate a trigger current of the SCR; and
a second stress layer on the top surface of the semiconductor substrate, the second stress layer configured to transfer a second mechanical stress to the second well,
wherein the first mechanical stress and the second mechanical stress have opposite polarities selected from tensile stress or compressive stress.
2. The device structure of claim 1 wherein the first well is laterally positioned in the semiconductor substrate to adjoin the second well along a first p-n junction.
3. The device structure of claim 2 wherein the anode is a first doped region in the first well and has the second conductivity type, the cathode is a second doped region in the second well and has the first conductivity type, and the first and second doped regions are disposed in the current-carrying path between the anode and the cathode.
4. The device structure of claim 3 wherein the first doped region is disposed between the first well and the top surface of the semiconductor substrate, and the second doped region is disposed between the second well and the top surface of the semiconductor substrate.
5. The device structure of claim 1 further comprising:
an input/output pad coupled to the anode; and
a ground pad coupled to the cathode.
6. The device structure of claim 1 wherein the first layer is comprised of silicon nitride including an internal stress opposite in polarity to the first mechanical stress.
7. The device structure of claim 1 wherein the trigger current is reduced in response to the first mechanical stress.
8. The device structure of claim 1 wherein the trigger current is increased in response to the first mechanical stress.
9. A device structure formed using a semiconductor substrate having a top surface, the device structure comprising:
a silicon controlled rectifier (SCR) including an anode, a cathode, a first well in the semiconductor substrate and having a first conductivity type, and a second well in the semiconductor substrate and having a second conductivity type opposite to the first conductivity type, the first well and the second well disposed in a current-carrying path between the anode and the cathode;
a first stress layer on the top surface of the semiconductor substrate, the first stress layer located at a position on the top surface of the semiconductor substrate and configured to cause a first mechanical stress in the first well at a level sufficient to modulate a trigger current of the SCR; and
a trigger network including a trigger diode string coupled in series with the first well,
wherein the level of the first mechanical stress from the first stress layer is sufficient adjust an electrical resistance of the first well to modulate the trigger current to be equal to a selected value.
10. The device structure of claim 9 further comprising:
a second stress layer on the top surface of the semiconductor substrate, the second stress layer configured to transfer a second mechanical stress to the second well.
11. The device structure of claim 10 wherein the first mechanical stress and the second mechanical stress have opposite polarities selected from tensile stress or compressive stress.
12. The device structure of claim 9 wherein the first well is laterally positioned in the semiconductor substrate to adjoin the second well along a first p-n junction.
13. The device structure of claim 12 wherein the anode is a first doped region in the first well and has the second conductivity type, the cathode is a second doped region in the second well and has the first conductivity type, and the first and second doped regions are disposed in the current-carrying path between the anode and the cathode.
14. The device structure of claim 13 wherein the first doped region is disposed between the first well and the top surface of the semiconductor substrate, and the second doped region is disposed between the second well and the top surface of the semiconductor substrate.
15. The device structure of claim 9 further comprising:
an input/output pad coupled to the anode; and
a ground pad coupled to the cathode.
16. The device structure of claim 9 wherein the first layer is comprised of silicon nitride including an internal stress opposite in polarity to the first mechanical stress.
17. The device structure of claim 9 wherein the trigger current is reduced in response to the first mechanical stress.
18. The device structure of claim 9 wherein the trigger current is increased in response to the first mechanical stress.