Locally raised epitaxy for improved contact by local silicon capping during trench silicide processings
A low resistance contact to a finFET source/drain can be achieved by forming a defect free surface on which to form such contact. The fins of a finFET can be exposed to epitaxial growth conditions to increase the bulk of semiconductive material in the source/drain. Facing growth fronts can merge or can form unmerged facets. A dielectric material can fill voids within the source drain region. A trench spaced from the finFET gate can expose the top portion of faceted epitaxial growth on fins within said trench, such top portions separated by a smooth dielectric surface. A silicon layer selectively formed on the top portions exposed within the trench can be converted to a semiconductor-metal layer, connecting such contact with individual fins in the source drain region.
1. A method to form a finFET, the method comprising:
on an initial structure that includes (a) a gate formed over a set of fins on a substrate and (b) at least two of said set extend into a S/D region adjacent to said gate, forming epitaxial material on said at least two of said set within said S/D region;
covering said epitaxial material with a dielectric layer;
forming a cavity in said dielectric material to expose a top area of said epitaxial material, wherein said cavity extends generally parallel to said gate and is separated from said gate by a region of said dielectric material;
growing a silicon cap on said top area; and
forming a first conductive bar in said cavity.
2. The method of claim 1 wherein the gate of the initial structure is a dummy gate, the method further comprising forming a functional gate after removing the dummy gate.
3. The method of claim 1 wherein said at least two include facing sidewalls, the method further comprising:
stopping the step of forming epitaxial material before growth from each of said facing sidewalls merge.
4. The method of claim 3 wherein the top surface of said epitaxial material is sloped relative to the substrate and wherein said cavity is formed to a depth such that upper portions of said top surface are exposed and lower portions of said top surface remain covered by said dielectric material.
5. The method of claim 1 wherein said epitaxial material is formed by exposing said initial structure to conditions for in-situ doped epitaxial growth.
6. The method of claim 1 further comprising forming a reinforcing spacer before covering said epitaxial material with dielectric material.
7. The method of claim 1 wherein said epitaxial material includes a lower surface that is sloped relative to the substrate, the method further comprising filling between said lower surface and said substrate by said dielectric material.
8. The method of claim 1 wherein said cavity is a first cavity that exposes p-type doped epitaxial material, the method further comprising:
after growing a silicon cap layer on said top area within said first cavity, forming a second cavity in said dielectric material to expose n-type doped epitaxial material, wherein said second cavity extends generally parallel to said gate and is separated from said gate by a region of said dielectric material;
and forming said first conductive bar and also forming a second conductive bar by depositing a metal-silicide forming metal within said first and second cavities.