SRAM global precharge, discharge, and sense
An SRAM includes a global bit line, an SRAM cell, precharge logic, discharge logic, and sense logic. The SRAM cell stores a first logical value or a second logic value and is coupled to the global bit line. The precharge logic may charge the global bit line to a precharge voltage for a non-read operation and a boosted voltage that is greater than a reference voltage for a read operation. The discharge logic may either maintain the global bit line at the boosted voltage for the first logical value or discharge the global bit line to a discharge voltage that is less than the reference voltage for the second logical value. The sense logic may output the first logical value when the global bit line has the boosted voltage or may output the second logical value when the global bit line has the discharge voltage.
1. A method for reading an SRAM cell connected to a local bit line and storing one of a first logical value or a second logical value in a domino SRAM, comprising:
precharging a global bit line to a non-zero precharge voltage for a period prior to a non-read operation;
charging the global bit line to a boosted voltage that is greater than the precharge voltage for a period prior to a read operation;
maintaining the global bit line at the boosted voltage for reading the first logical value stored in the SRAM cell;
discharging the global bit line to a discharge voltage that is less than the precharge voltage for reading the second logical value stored in the SRAM cell;
sensing the boosted voltage on the global bit line for the first logical value and the discharge voltage on the global bit line for the second logical value;
and outputting the first logical value in response to sensing the boosted voltage on the global bit line and outputting the second logical value in response to sensing the discharge voltage on the global bit line.
2. The method of claim 1 , wherein outputting the first logical value comprises outputting the complement of the first logical value and outputting the second logical value comprises outputting the complement of the second logical value.
3. The method of claim 1 , further comprising precharging the global bit line to a write voltage during a write operation.
4. The method of claim 3 , wherein the write voltage is less than the precharge voltage.