MOSFET with recessed channel film and abrupt junctions
MOSFETs and methods for making MOSFETs with a recessed channel and abrupt junctions are disclosed. The method includes creating source and drain extensions while a dummy gate is in place. The source/drain extensions create a diffuse junction with the silicon substrate. The method continues by removing the dummy gate and etching a recess in the silicon substrate. The recess intersects at least a portion of the source and drain junction. Then a channel is formed by growing a silicon film to at least partially fill the recess. The channel has sharp junctions with the source and drains, while the unetched silicon remaining below the channel has diffuse junctions with the source and drain. Thus, a MOSFET with two junction regions, sharp and diffuse, in the same transistor can be created.
1. A semiconductor on insulator (SOI) substrate comprising:
a bottom bulk semiconductor layer;
a buried insulator layer on the bottom bulk semiconductor layer;
an SOI layer on the buried insulator layer;
a doped source that extends throughout a thickness of the SOI layer;
a doped drain that extends throughout the thickness of the SOI layer;
a channel film disposed between the doped source and the doped drain, with a top surface of the channel film disposed below a top surface of the doped source and the doped drain; and
a remaining portion of the SOI layer under the channel film;
wherein the channel film abuts the doped source and the doped drain at both side and bottom surfaces thereof to form a sharp channel-source junction and a sharp channel-drain junction; and
wherein the remaining portion of the SOI layer under the channel film abuts the doped source and abuts the doped drain to form a diffuse SOI-source junction and a diffuse SOI-drain junction such that the diffuse junctions have a junction width of about twice that of the sharp junctions along a horizontal orientation of the SOI layer.
2. The substrate of claim 1 , wherein a channel film thickness is greater than a thickness of the remaining portion of the semiconductor-on-insulator layer under the channel film.
3. The substrate of claim 1 , wherein the sharp junctions have a dopant gradient from about 0.5 nm per decade to about to 3 nm per decade and ranges there between.
4. The substrate of claim 1 , wherein the diffuse junctions have a dopant gradient from about 3 nm per decade to about 10 nm per decade and ranges there between.
5. A metal oxide semiconductor field effect transistor (MOSFET) comprising:
a bottom bulk semiconductor layer;
a buried insulator layer on the bottom bulk semiconductor layer;
a semiconductor on insulator (SOI) layer on the buried insulator layer;
a doped source that extends throughout a thickness of the semiconductor-on-insulator layer;
a doped drain that extends throughout the thickness of the SOI layer;
an insulator layer above the doped source and doped drain;
a channel film disposed between the doped source and the doped drain, with a top surface of the channel film disposed below a top surface of the doped source and the doped drain;
a remaining portion of the SOI layer under the channel film;
an opening in the insulator wherein the opening is above at least a portion of the channel film;
a high dielectric constant material in contact with at least a portion of the channel film; and
a metal gate in contact with the high dielectric constant material;
wherein the channel film abuts the doped source and the doped drain at both side and bottom surfaces thereof to form a sharp channel-source junction and a sharp channel-drain junction; and
wherein the remaining portion of the SOI layer under the channel film abuts the doped source and abuts the doped drain to form a diffuse SOI-source junction and a diffuse SOI-drain junction such that the diffuse junctions have a junction width of about twice that of the sharp junctions along a horizontal orientation of the SOI layer.
6. The MOSFET of claim 5 , further comprising:
a gate width which is from about 5 nm to about 25 nm and ranges there between.
7. The MOSFET of claim 5 , wherein:
the channel film has a plurality of sidewalls;
the high dielectric constant material has a plurality of outer surfaces; and
at least one of the channel film sidewalls aligns vertically with one of the dielectric constant material outer surfaces.
8. The MOSFET of claim 5 , wherein:
the channel film has a channel film width; and
the channel film width is from about 5 nm to about 50 nm and ranges there between.
9. The MOSFET of claim 5 , further comprising:
a raised source above the doped source; and
a raised drain above the doped drain.