Self-aligned contacts for high k/metal gate process flow
A semiconductor structure is provided that includes a semiconductor substrate having a plurality of gate stacks located thereon. Each gate stack includes a high k gate dielectric layer, a work function metal layer and a conductive metal. A spacer is located on sidewalls of each gate stack and a self-aligned dielectric liner is present on an upper surface of each spacer. A bottom surface of each self-aligned dielectric liner is present on an upper surface of a semiconductor metal alloy. A contact metal is located between neighboring gate stacks and is separated from each gate stack by the self-aligned dielectric liner. The structure also includes another contact metal having a portion that is located on and in direct contact with an upper surface of the contact metal and another portion that is located on and in direct contact with the conductive metal of one of the gate stacks.
1. A method of forming a semiconductor structure comprising:
providing a structure including a plurality of sacrificial gate stacks located on a surface of a semiconductor substrate, wherein each sacrificial gate stack includes a spacer located on a vertical sidewall thereof, and wherein a metal semiconductor alloy layer is at least located on an exposed surface of the semiconductor substrate between neighboring sacrificial gate stacks;
forming a self-aligned dielectric liner on exposed surfaces of each sacrificial gate stack, said spacer and said metal semiconductor alloy layer;
forming a planarized dielectric material having a contact opening that is partially filled with a recessed contact metal, wherein portions of the self-aligned dielectric liner are removed from horizontal surfaces within the contact opening;
replacing each sacrificial gate stack of said plurality of sacrificial gate stacks with a permanent gate stack thereby providing a plurality of permanent gate stacks on said surface of said semiconductor substrate, wherein each permanent gate stack includes a high k gate dielectric layer, a work function metal layer and a conductive metal, wherein an uppermost surface of each of said high k gate dielectric layer, said work function metal layer and said conductive metal is coplanar with each other, and wherein said uppermost surface of each of said high k gate dielectric layer, said work function metal layer and said conductive metal is located beneath an uppermost surface of both of said planarized dielectric material and said spacer; and
forming another contact metal having a first portion that is located on and in direct contact with an upper surface of the recessed contact metal and a second portion that is located on and in direct contact with said uppermost surface of each of said high k gate dielectric layer, said work function metal layer and said conductive metal of one of the permanent gate stacks, wherein said forming another contact metal comprises:
forming a hard mask layer atop said semiconductor substrate, each permanent gate stack and said recessed contact metal;
forming a patterned resist having a gate opening on said hard mask layer;
transferring said gate opening into said hard mask layer to provide a patterned hard mask structure containing said gate opening;
removing said patterned resist;
forming another patterned resist having a line opening atop said patterned hard mask structure;
transferring said line opening to said patterned hard mask structure; and
removing said another patterned resist.
2. The method of claim 1 wherein said gate opening in said patterned hard mask structure is located above said uppermost surface of said conductive metal layer of each permanent gate stack, while a portion of the line opening in said patterned hard mask structure is located above the recessed contact metal.
3. The method of claim 1 wherein said forming a planarized dielectric material having a contact opening that is partially filled with a recessed contact metal comprises forming a planarization dielectric material, forming said contact opening within said planarization dielectric material, removing said self-aligned dielectric liner from said horizontal surfaces within said contact opening, filling the contact opening with a contact metal, recessing the contact metal, and planarizing the planarization dielectric material.
4. The method of claim 3 further comprising forming a planarized oxide cap atop the recessed contact metal after recessing the contact metal and removing the planarized oxide cap prior to forming the another contact metal.
5. The method of claim 1 wherein said conductive metal is comprised of an elemental metal, an alloy of an elemental metal or a metal silicide.
6. The method of claim 1 wherein said high k gate dielectric layer is comprised of HfO 2 , ZrO 2 , La 2 O 3 , Al 2 O 3 , TiO 2 , SrTiO 3 , LaAlO 3 , Y 2 O 3 , HfO x N y , ZrO x N y , La 2 O x N y , Al 2 O x N y , TiO x N y , SrTiO x N y , LaAlO x N y , Y 2 O x N y , a silicate thereof, or an alloy thereof, wherein each value of x is independently from 0.5 to 3 and each value of y is independently from 0 to 2.
7. The method of claim 1 wherein said work function metal layer comprises a silicon valence band edge metal.
8. The method of claim 1 wherein said work function metal layer comprises a silicon conduction band edge metal.
9. The method of claim 1 wherein said self-aligned dielectric liner is comprised of a high k dielectric material whose dielectric constant is greater than silicon oxide.
10. The method of claim 9 wherein said high k dielectric material is comprised of HfO 2 , ZrO 2 , La 2 O 3 , Al 2 O 3 , TiO 2 , SrTiO 3 , LaAlO 3 , Y 2 O 3 , HfO x N y , ZrO x N y , La 2 O x N y , Al 2 O x N y , TiO x N y , SrTiO x N y , LaAlO x N y , Y 2 O x N y , a silicate thereof, or an alloy thereof, wherein each value of x is independently from 0.5 to 3 and each value of y is independently from 0 to 2.
11. The method of claim 1 wherein said high k gate dielectric layer and said work function metal layer are U-shaped.