Structures and methods for improving solder bump connections in semiconductor devices
Structures with improved solder bump connections and methods of fabricating such structures are provided herein. The structure includes a via formed in a dielectric layer to expose a contact pad and a capture pad formed in the via and over the dielectric layer. The capture pad has openings over the dielectric layer to form segmented features. The solder bump is deposited on the capture pad and the openings over the dielectric layer.
1. A lead free solder bump structure, comprising:
a via formed in a dielectric layer to expose a contact pad;
a capture pad formed in the via and over the dielectric layer, the capture pad having openings over the dielectric layer to form segmented features; and
a solder bump deposited on the capture pad and the openings over the dielectric layer.
2. The structure of claim 1 , further comprising a laminate bonded to the solder bump.
3. The structure of claim 1 , wherein the solder bump is a lead free solder bump.
4. The structure of claim 1 , wherein the capture pad is an under bump metallurgy or ball limiting metallurgy having a refractory metal base layer and a diffusion barrier to layer, and the contact pad is Al.
5. The structure of claim 1 , wherein the dielectric layer is a photosensitive polyimide formed over other insulative layers having pads and/or wires and metal vias.
6. The structure of claim 1 , wherein the openings are of various sizes and shapes.
7. The structure of claim 1 , wherein openings are formed in the capture pad structure over the dielectric layer to form a plurality of capture pad structure openings surrounding the via and the solder bump is over capture pad structure and between the segmented features.
8. The structure of claim 7 , wherein the capture pad structure comprises layers including one of:
a nickel material sandwiched between a gold layer and a barrier layer; and
a TiW/Cu/Ni structure.
9. The structure of claim 8 , wherein the barrier layer is a TiW barrier layer.
10. The structure of claim 1 , wherein the solder bump covers no more than one via.