Self aligned contact with improved robustness
A semiconductor device is provided that includes a gate structure that is present on a channel portion of a semiconductor substrate that is present between a source region and a drain region. The gate structure includes at least a gate conductor and a gate sidewall spacer that is adjacent to the at least one gate conductor. An upper surface of the gate conductor is recessed relative to an upper surface of the gate sidewall spacer. A multi-layered cap is present on the upper surface of the gate conductor. The multi-layered cap includes a high-k dielectric material and a dielectric cap spacer that is present on a portion of the high-k dielectric material that is present on the sidewall of the gate sidewall spacer.
1. A semiconductor device comprising:
a gate structure that is present on a channel portion of a semiconductor substrate that is present between a source region and a drain region, wherein the gate structure includes at least a gate conductor and a gate sidewall spacer that is adjacent to the at least one gate conductor, wherein an upper surface of the gate conductor is recessed relative to an upper surface of the gate sidewall spacer; and
a multi-layered cap on the upper surface of the gate conductor, wherein the multi-layered cap includes a high-k dielectric material, wherein the multi-layered cap also includes a dielectric cap spacer that is present on a portion of the high-k dielectric material that is present on the sidewall of the gate sidewall spacer, wherein the high-k dielectric material includes a lower portion, a first lateral sidewall, and a second lateral sidewall, wherein the lower portion of the high-k dielectric material is located on an upper surface of the gate conductor, and wherein the first and second lateral sidewalls of the high-k dielectric material are spaced apart and extend vertically upward from the lower portion of the high-k dielectric material along the gate sidewall spacer in a direction away from the semiconductor substrate, wherein a first surface of the dielectric cap spacer is located in direct physical contact with the second lateral sidewall of the high-k dielectric material, and wherein a sidewall of the dielectric cap spacer located opposite to the first surface of the dielectric cap spacer has a convex curvature relative to the second lateral sidewall of the high-k dielectric material.
2. The semiconductor device of claim 1 , wherein the gate structure includes a gate dielectric that is present between the gate conductor and the channel portion of a semiconductor substrate, wherein the gate dielectric has vertical portions that extend above the upper surface of the gate conductor.
3. The semiconductor device of claim 1 , wherein a source region and a drain region are present in the semiconductor substrate on opposing sides of the channel portion of the semiconductor substrate.
4. The semiconductor device of claim 1 , wherein the high-k dielectric material comprises hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate or a combination thereof.
5. The semiconductor device of claim 1 , wherein the dielectric cap spacer comprises silicon oxide, silicon nitride, silicon oxynitride or a combination thereof.
6. The semiconductor device of claim 1 , further comprising an interlevel dielectric layer located adjacent the gate structure, wherein an upper surface of the interlevel dielectric layer is coplanar with an uppermost surface of the multi-layered gate cap.
7. The semiconductor device of claim 1 , wherein the multi-layered cap further comprises a dielectric fill material in direct physical contact with the first lateral sidewall, the second lateral sidewall and the lower portion of the high-k dielectric material, wherein upper surfaces of the first and second lateral sidewalls the high-k dielectric material are coplanar with an upper surface of the dielectric fill material, and wherein a bottom surface of the lower portion of the high-k dielectric material is in direct physical contact with the upper surface of the gate conductor.
8. The semiconductor device of claim 1 , wherein the multi-layered cap further comprises an intermediate dielectric layer in direct physical contact with the first lateral sidewall, the second lateral sidewall and the lower portion of the high-k dielectric material, and a dielectric fill material in direct physical contact with the intermediate dielectric layer, wherein upper surfaces of the first and second lateral sidewalls of the high-k dielectric material, the intermediate dielectric layer and the dielectric fill material are coplanar with each other, and wherein a bottom surface of the lower portion of the high-k dielectric material is in direct physical contact with the upper surface of the gate condutor.
9. The semiconductor device of claim 6 , further comprising another interlevel dielectric layer located on the interlevel dielectric layer, wherein an interconnect contact is present in the another interlevel dielectric layer and the interlevel dielectric layer.
10. The semiconductor device of claim 9 , wherein a portion of the interconnect contact is located on a sidewall of the dielectric cap spacer.
11. A semiconductor device comprising:
a gate structure that is present on a channel portion of a semiconductor substrate that is present between a source region and a drain region, wherein the gate structure includes a gate dielectric, at least a gate conductor and a gate sidewall spacer having sidewalls in direct contact with vertical sidewalls of the gate dielectric, wherein an upper surface of the gate conductor is recessed relative to an upper surface of the gate sidewall spacer; and
a multi-layered cap on the upper surface of the gate conductor, wherein the multi-layered cap includes a high-k dielectric material that is present on a portion of a sidewall of the gate sidewall spacer that extends beyond an upper surface of the gate conductor, wherein the multi-layered cap also includes a dielectric cap spacer that is present on a portion of the high-k dielectric material that is present on the sidewall of the gate sidewall spacer, wherein the high-k dielectric material includes a lower portion, a first lateral sidewall, and a second lateral sidewall, wherein the lower portion of the high-k dielectric material is located on an upper surface of the gate conductor, and wherein the first and second lateral sidewalls of the high-k dielectric material are spaced apart and extend vertically upward from the lower portion of the high-k dielectric material along the gate sidewall spacer in a direction away from the semiconductor substrate, wherein a first surface of the dielectric cap spacer is located in direct physical contact with the second lateral sidewall of the high-k dielectric material, and wherein a sidewall of the dielectric cap spacer located opposite to the first surface of the dielectric cap spacer has a convex curvature relative to the second lateral sidewall of the high-k dielectric material.
12. The semiconductor device of claim 11 , wherein the high-k dielectric material comprises hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate or a combination thereof.
13. The semiconductor device of claim 11 , wherein the dielectric cap spacer comprises silicon oxide, silicon nitride, silicon oxynitride or a combination thereof.
14. The semiconductor device of claim 11 , further comprising an interlevel dielectric layer located adjacent the gate structure, wherein an upper surface of the interlevel dielectric layer is coplanar with an uppermost surface of the multi-layered gate cap.
15. The semiconductor device of claim 11 , wherein the multi-layered cap further comprises a dielectric fill material in direct physical contact with the first lateral sidewall, the second lateral sidewall and the lower portion of the high-k dielectric material, wherein upper surfaces of the first and second lateral sidewalls of the high-k dielectric material are coplanar with an upper surface of the dielectric fill material, and wherein a bottom surface of the lower portion of the high-k dielectric material is in direct physical contact with the upper surface of the gate conductor.
16. The semiconductor device of claim 11 , wherein the multi-layered cap further comprises an intermediate dielectric layer in direct physical contact with the first lateral sidewall, the second lateral sidewall and the lower portion of the high-k dielectric material, and a dielectric fill material in direct physical contact with the intermediate dielectric layer, wherein upper surfaces of the first and second lateral sidewalls of the high-k dielectric material, the intermediate dielectric layer and the dielectric fill material are coplanar with each other, and wherein a bottom surface of the lower portion of the high-k dielectric material is in direct physical contact with the upper surface of the gate conductor.
17. The semiconductor device of claim 14 , further comprising another interlevel dielectric layer located on the interlevel dielectric layer, wherein an interconnect contact is present in the another interlevel dielectric layer and the interlevel dielectric layer.
18. The semiconductor device of claim 17 , wherein a portion of the interconnect contact is located on a sidewall of the dielectric cap spacer.