Non-volatile memory having 3D array architecture with staircase word lines and vertical bit lines and methods thereof
In a 3D nonvolatile memory with memory elements arranged in a three-dimensional pattern defined by rectangular coordinates having x, y and z-directions and with a plurality of parallel planes from a bottom plane to a top plane stacked in the z-direction over a semiconductor substrate; a plurality of local bit lines elongated in the z-direction through the plurality of layers and arranged in a two-dimensional rectangular array of bit line pillars having rows in the x-direction and columns in the y-direction; the 3D nonvolatile memory further having a plurality of staircase word lines spaced apart in the y-direction and between and separated from the plurality of bit line pillars at a plurality of crossings, individual staircase word lines each having a series of alternating steps and risers elongated respectively in the x-direction and z-direction traversing across the plurality of planes in the z-direction with a segment in each plane.
1. A non-volatile memory, comprising:
memory elements arranged in a three-dimensional pattern defined by rectangular coordinates having x, y and z-directions and with a plurality of parallel planes from a bottom plane to a top plane stacked in the z-direction over a semiconductor substrate;
a plurality of local bit lines elongated in the z-direction through the plurality of parallel planes and arranged in a two-dimensional rectangular array of bit line pillars having rows in the x-direction and columns in the y-direction;
a plurality of staircase word lines spaced apart in the y-direction and between and separated from the plurality of bit line pillars at a plurality of crossings, each individual staircase word lines of the said plurality of staircase word lines having a series of alternating steps and risers elongated respectively in the x-direction and z-direction traversing across the plurality of planes in the z-direction with a segment in each plane; and
a plurality of non-volatile re-programmable memory elements individually connected through circuits between the bit line pillars and the staircase word lines adjacent the crossings thereof.
2. The non-volatile memory as in claim 1 , wherein:
adjacent staircase word lines of said plurality of staircase word lines are staggered and spaced apart in the x-direction by a predetermined offset.
3. The non-volatile memory as in claim 2 , wherein:
said predetermined offset is a spacing between two bit line pillars of the row of bit line pillars.
4. The non-volatile memory as in claim 2 , wherein:
said predetermined offset is half of a spacing between two bit line pillars of the row of bit line pillars.
5. The non-volatile memory as in claim 1 , wherein:
each segment of the staircase word line crosses a segment of bit line pillars; and
the segment of staircase word line has at least one riser raising the segment prior to crossing a last one of the bit line pillars in the segment.
6. The non-volatile memory as in claim 1 , wherein:
each segment of the staircase word line crosses a segment of bit line pillars; and
the segment of staircase word line has a riser after crossing each of the bit line pillars in the segment.
7. The non-volatile memory as in claim 1 , further comprising
an associated word line driver above the top plane connected to each staircase word line.
8. The non-volatile memory as in claim 7 , wherein:
the associated word line driver has a size along the x-direction fitting within a segment.
9. The non-volatile memory as in claim 1 , further comprising
an associated word line driver below the bottom plane connected to each staircase word line.
10. The non-volatile memory as in claim 9 , wherein:
the associated word line driver has a size along the x-direction fitting within a segment.
11. The non-volatile memory as in claim 1 , further comprising
a plurality of global conductive lines in the y-direction; and
a row of pillar select devices in the x-direction below a selected row of bit line pillar in the x-direction arranged to switch the selected row of bit line pillars to corresponding global conductive lines in the y-direction.
12. The non-volatile memory as in claim 1 , wherein:
said plurality of non-volatile re-programmable memory elements each has a resistance that reversibly shift in value in response to a voltage applied to or current passed through each memory element.
13. A method of operating a non-volatile memory, comprising:
providing memory elements arranged in a three-dimensional pattern defined by rectangular coordinates having x, y and z-directions and with a plurality of parallel planes stacked in the z-direction over a semiconductor substrate;
providing a plurality of local bit lines elongated in the z-direction through the plurality of parallel planes and arranged in a two-dimensional rectangular array of bit line pillars having rows in the x-direction and columns in the y-direction;
providing a plurality of staircase word lines spaced apart in the y-direction and between and separated from the plurality of bit line pillars at a plurality of crossings, each individual staircase word lines of the said plurality of staircase word lines having a series of alternating steps and risers elongated respectively in the x-direction and z-direction traversing across the plurality of planes in the z-direction with a segment in each plane;
providing a plurality of non-volatile re-programmable memory elements individually connected through circuits between the bit line pillars and the staircase word lines adjacent the crossings thereof; and
wherein voltages are applied through the plurality of local bit lines and the plurality of staircase word lines to effect memory operations on a selected group of non-volatile re-programmable memory elements.
14. The method as in claim 13 , wherein:
adjacent staircase word lines of said plurality of staircase word lines are staggered and spaced apart in the x-direction by a predetermined offset.
15. The method as in claim 14 , wherein:
said predetermined offset is a spacing between two bit line pillars of the row of bit line pillars.
16. The method as in claim 14 , wherein:
said predetermined offset is half of a spacing between two bit line pillars of the row of bit line pillars.
17. The method as in claim 13 , wherein:
each segment of the staircase word line crosses a segment of bit line pillars; and
the segment of staircase word line has at least one riser raising the segment prior to crossing a last one of the bit line pillars in the segment.
18. The method as in claim 13 , wherein:
each segment of the staircase word line crosses a segment of bit line pillars; and
the segment of staircase word line has a riser after crossing each of the bit line pillars in the segment.
19. The method as in claim 13 , further comprising
an associated word line driver above the top plane connected to each staircase word line.
20. The method as in claim 19 , wherein:
the associated word line driver has a size along the x-direction fitting within a segment.
21. The method as in claim 13 , further comprising
an associated word line driver below the bottom plane connected to each staircase word line.
22. The method as in claim 21 , wherein:
the associated word line driver has a size along the x-direction fitting within a segment.